Xilinx Academy M1.5i Advanced Implementation Tools Training Rohit Sawhney

1. Xilinx Academy M1.5i Advanced Implementation Tools Training Rohit Sawhney

2. AGENDA • Intro Lab / Demo • M1 Constraints Lab • Map Lab • M1 PAR (Effort Levels and MPPR) • Place and Route Lab / Re-Entrant Routing Lab • Cleanup Routing Lab (optional) • Floorplanner Lab (Area Based Floorplanning - optional) • EPIC Lab (Editing a Design / Adding a Probe Pin - optional) • Timing Improvement Lab • Guide Lab (optional) • Summary

3. M1 Constraints Understanding Timing and Placement Constraints

4. M1 Design Flow UCF XNF/EDIF netlist User Constraints File NGDBUILD Flatten Hierarchical Design .NGD MAP Logical to Physical translation Group LUTs and FFs into CLBs Optional: Reports block delays TRCE .NCD .PCF Static Timing Estimates PAR BITGEN Layout of Physical Design Routes Physical Design Generates configuration file .NCD .BIT

5. X Y Z<0:9> Pin 2 Pin Speed What Needs Constraining? • Internal clock speed for one or more clocks • I/O speed • Logic using multi-cycle clocks • Pin to Pin timing • Pin Locations & Logic Locations Clk & CE Speed I/O Speed I/O Speed Pin Locations D Q D Q OUT1 1 Level of Logic CLK Logic Locations 2 Levels of Logic OUT2 Pin Locations

6. Types of constraints supported • Timing Constraints • Specify delay along logic paths • Allows both “quick and dirty” and “highly detailed” timing control • Location Constraints • Specify location of components on FPGA • Specify mapping constraints INST FLOP1 BLKNM=ABC INST MY_FMAP BLKNM=ABC INST FLOP2 BLKNM=ABC

7. Timing Constraints (I) Using PERIOD and OFFSET constraints

8. Period Constraint - Definition PERIOD • PERIOD is the duration of the clock and can be configured to have different duty cycles • Derived clocks can be defined as a function of another clock (*,/) • PERIOD is preferred over other explicit constraints (FROM:TO) ; M1 tools will have a faster runtime. PERIOD should cover most of design.

9. The Period Constraint • Period : This constraint covers all paths from a PAD to a synchronous element (FF, Latch or synchronous RAM), and paths between synchronous elements which are clocked by the referenced net. (Every synchronous element is effectively identified by forward propagation.) • It does not cover paths to output pads, but does cover input pads. • What Constraints Editor writes into UCF file: • Single clock designs: NET “CLKA_IN” TNM_NET = “CLKA_IN”; …...(make a group) TIMESPEC “TS_CLKA_IN” = PERIOD “CLKA_IN” 20 NS HIGH 50; …..(apply PERIOD to the group) • Multiple Related Clock Designs (after CLKB_IN has also been defined): TIMESPEC “TS_CLKB2CLKA” = FROM “CLKB_IN” TO CLKA_IN” 15 NS; FLOP LATCH D Q D Q OUT1 G PERIOD=30 CLK RAM OUT2 Path controlled by PERIOD Forward propagation path

10. The OFFSET IN - ‘BEFORE’ constraint OFFSET = IN 20nS BEFORE CLK FPGA UPSTREAM DEVICE DATA Din CLK CLK This says, Data will be valid here, 20nS BEFORE the clock arrives here. In other words: “The Data to be registered in the FPGA will be available on the FPGA’s input Pad 20ns BEFORE the clock pulse is seen by the FPGA’s clock pad.” Therefore, the M1 tools will calculate: Maximum_Allowable_Internal_P2S_Delay = OFFSET + internal_CLK_delay. The tools can automatically calculate and control internal data and clock delays to meet TsuFF Data registered in FPGA on this edge. 20ns Data Out of DEV1 on this edge. Valid Tbufg Designer must ensure that T(clock_period) - 20ns = ext-delay TsuFF Internal delay Valid

11. The OFFSET OUT - ‘AFTER’ constraint OFFSET = OUT 22nS AFTER CLK DATA FPGA DOWNSTREAM DEVICE This says, Data will be valid here, 22nS AFTER the clock arrives here!….. In other words: “The Data to be registered in the Downstream Device will be available on the FPGA’s output Pad 22ns AFTER the clock pulse is seen by the FPGA.” (Maximum_Allowable_Internal_Dout_Delay = OFFSET - internal_CLK_delay). Designer must ensure that T(clock_period) - 22ns = ext-delay ext-delay = sufficient time for external delays involved with meeting DEV2 setup time. 22ns Data clocked into DEV2 on this edge. Valid Data Out of FPGA on this edge.

12. Timing Constraints (II) Using FROM:TO and other constraints

13. Timing Path Keywords • Timing constraints are applied to logic paths • Logic paths typically start and stop at pads, registers, latches, and RAM • M1 recognizes the following keywords to define endpoints or time groups: PADS All I/O pads FFS All flip-flops LATCHES All latches RAMS All RAM elements • Keywords can be used globally, and to create design sub-groups

14. TS_P2P Basic Global Timing Constraints( using the FROM-TO Syntax) UCF TIMESPEC command using default keywords: TIMESPEC TS_C2S=FROM:FFS:TO:FFS:30; TIMESPEC TS_P2S=FROM:PADS:TO:FFS:25; TIMESPEC TS_P2P=FROM:PADS:TO:PADS:26; TIMESPEC TS_C2P=FROM:FFS:TO:PADS:9; TS_P2S TS_C2S TS_C2P D Q D Q OUT1 CLK OUT2

15. Basic Global Timing Constraints( using the FROM-TO Syntax) TIMESPEC TS_F2F=FROM:FFS:TO:FFS:30; • The word TIMESPEC defines the type of specification • The Spec’s name must start with “TS” any alpha-numeric after TS is fine. Recommendation: Make the name something you will remember later. • FROM: designates the origin of the path • TO: designates the destination of the path • 30; in ns by default, is the specification. You can use MHz, or even another time spec like TS_C2S/2 or TS_C2S*2

16. Using TNM to create Groups NET clock TNM=clk_group; • Any Keyword element can be made into a ‘group’ for timing purposes • In this example the net ‘clock’ is traced forward to the two flip-flop (FFS). • These flip-flops are ‘timing-named’ (TNM) with the name ‘clk_group’. • They can now be referenced by this TNM in TIMESPECs D Q D Q OUT1 CLOCK OUT2

17. Using TNM to create Groups(cont.) NET clock TNM=clk_group; • These timing groups can overlap, meaning a FFS, LATCHES, RAMS, or PADS can belong to multiple groups if necessary to describe your design’s timing • Time constraints are case sensitive (TNM=abc  TNM=ABC) • No longer an issue due to the intro of the Constraints Editor ! • Groups are ideal for identifying groups of logic that work at different speeds…….(multi-cycle paths and other slow exceptions).

18. Using TNM_NET to create Groups NET clock TNM_NET=clk_group; • TNM_NET is equivalent to TNM on a net except for pad nets. • In M1.4, when placing a TNM on a pad net, the TNM would locate itself on the pad and not trace forward through the buffer to the next synchronous element. TNM_NET was created for this purpose in M1.5. If you place a TNM_NET on a pad net, it will trace through the buffer to the next synchronous element. • TNM_NET is extremely useful for synthesis designs because the only meaningful net names are the ones directly connected to pads. • Constraints Editor automatically uses the TNM_NET syntax any time it is placing a timing name on a net.

19. Constraining Between Multiple Clock Domains • Define individual clocks (Constraints Editor - Global Tab) • NET “CLK_A” TNM_NET = “CLK_A”; • TIMESPEC “TS_CLK_A” = PERIOD “CLK_A” 20NS HIGH 50; • NET “CLK_B” TNM_NET = “CLK_B”; • TIMESPEC “TS_CLK_B” = PERIOD “CLK_B” TS_CLK_A*2; • Define phase difference between clocks (Constraints Editor - Advanced Tab) • TIMESPEC • TS_CLKA2CLKB=FROM “CLK_A” TO “CLK_B” 15NS; D Q D Q D Q OUT1 D Q CLK_A CLK_B

20. Timing Ignore (TIG) • TIG removes paths from analysis • Reduces reports by removing non-critical paths • This reduces the critical paths that PAR must deal with • TIG does change the percentage of connections covered in the timing report statistics

21. Disappearing Groups/ Paths • Empty Groups • Registers getting sucked into IOBs • Elements get trimmed in mapper • No Paths • Covered by another constraint (Priority) • TIG or Path Tracing Control has eliminated the paths

22. Timing Constraint Priority • Within a particular source: • Highest PriorityTiming ignores (TIG) FROM:THRU:TO specsSource and destination defined by user Source or destination defined by user Source and destination are pre-fined groupsFROM:TO specs Source and destination defined by user Source or destination defined by user Source and destination are pre-fined groups PERIOD specs • Lowest Priority • Note: OFFSET does not override and cannot be overridden. This will be addressed for M2.1i.

23. M1.5i Constraints Editor

24. Flow EDN NCF EDN NCF EDIF2NGD EDIF2NGD NGO NGO UCF NGDBUILD CONSTRAINTS EDITOR NGD MAP

25. DM/FE and CE

26. Graphical Constraints Editor • Guides user to the best constraint methodology • Eliminates need for user knowledge of syntax • Reduces need for user knowledge of nets and components of the design

27. Graphical Constraints EditorThree Easy Tabs! • Global Tab • Automatically displays every clock in the design • Simple entry of clock periods, setup times, and clock-to-pad • Ports Tab • Displays all I/O pins for the design • Simple entry of pin locations, setup, clock-to-pad • Advanced Tab • Enter more detailed constraints here • Create groups, use them in FROM:TO specs • Constraints Window at bottom displays UCF syntax • Editable and Read-Only Tabs • Can view, disable, and delete constraints

28. Global Tab

29. Ports Tab

30. AGENDA • Intro Lab / Demo • M1 Constraints Lab • Map Lab • M1 PAR (Effort Levels and MPPR) • Place and Route Lab / Re-Entrant Routing Lab • Cleanup Routing Lab (optional) • Floorplanner Lab (Area Based Floorplanning - optional) • EPIC Lab (Editing a Design / Adding a Probe Pin - optional) • Timing Improvement Lab • Guide Lab (optional) • Summary

31. M1 PAR Effort Levels and MPPR

32. Example 1MPPR Clock Period Distribution Median: 24.1ns Min: 22.7ns Max: 26.6ns Design: bdes2 4010XL

33. Example 1MPPR Performance and Timing Errors Design: bdes2 4010XL

34. Example 2MPPR Clock Period Distribution Median: 30.0ns Min: 28.2ns Max: 32.2ns Design: txr 4020XL

35. Example 3MPPR Clock Period Distribution Median: 21.9ns Min: 19.6ns Max: 28.4ns Design: mtpp 4013XL

36. Running Fewer Cost Tables Fewer cost tables have a smaller distribution but still useful to estimate performance potential.

37. MPPR Performance • Realized circuit performance is a random, “bell-shaped” distribution • Even running a limited set of cost tables is useful. • Covers enough of distribution to allow good prediction of ultimate performance potential • Impossible to predict which cost-table is best • MPPR is an advanced option; follow guidelines: • Don’t attempt on your 1st rev....only when design is about 95% complete • Push the limits (good placement->good routing->better timing results)

38. M1.5i FloorplannerTraining Lab

39. Training Lab Agenda • Understand basic floorplanner flow within M1 • Look at “traditional” BEL-level floorplanning in a more realistic, datapath oriented design • Learn about what characteristics make a design a good candidate for floorplanning • Advanced: Area-Based Floorplanning

40. Device / Platform Support • Supported Devices: • All 4K families (E, EX, XL, XV, Spartan) • 3K, 5K, and Virtex are not supported • Supported Platforms • Windows NT, Win95 • Solaris 2.5.x • HP

41. Invoking the Floorplanner • After selecting a particular revision, the Floorplanner can be invoked two ways: • Tools->Floorplanner • Click on the Floorplanner icon in the toolbar.

42. The Floorplanner / M1 Interface • Input Files: NGD, NCD • Output Files: • FNF : The actual floorplan - constraints and design hierarchy • MFP: Constraints file to control both packing and placement - used as input to mapper.

43. M1.5i Floorplanner Interface Diagram ngdbuild map design.ngd design.ngd design.ncd design.ngd design.mfp ncd2fnf ngd2fnf Floorplanner GUI map -fp design.fnf design.ncd M1.4 FPLAN GUI design.pcf design.fnf par

44. M1.5i Floorplanner *Preferred Flow* ngdbuild map design.ngd design.ngd design.ncd design.ngd par design.mfp design_p.ncd map -fp Floorplanner GUI design.ncd File->New Design: design ngd: design.ngd ncd: design_p.ncd fnf: <blank> design.pcf par design.fnf

45. AGENDA • Intro Lab / Demo • M1 Constraints Lab • Map Lab • M1 PAR (Effort Levels and MPPR) • Place and Route Lab / Re-Entrant Routing Lab • Cleanup Routing Lab (optional) • Floorplanner Lab (Area Based Floorplanning - optional) • EPIC Lab (Editing a Design / Adding a Probe Pin - optional) • Timing Improvement Lab • Guide Lab (optional) • Summary

46. Guide LabSimple Rules for Guide • Most appropriate for schematic designs • Low success rate for synthesis designs • Use leverage mode • Use guide PAR alone (not guided MAP) to reduce runtime. • Guide design must be “good”: • Meets timing • I/O locations are satisfactory

47. Summary • Constraints Editor • Global, Ports, and Advanced Tabs allow for easy entry of design constraints • Place and Route • Time well spent in placement pays off in routing. • Improve timing by increasing effort levels • Push the limits - 15-20% spread in performance with MPPR • Timing Analysis • Understand what to expect from the tools • Identify when to modify the design source • Reduce Logic Levels (Logic-to-Routing Ratio) • Long net delays (bad pin assignments?) • High fanout nets

48. AGENDA • Intro Lab / Demo • M1 Constraints Lab • Map Lab • M1 PAR (Effort Levels and MPPR) • Place and Route Lab / Re-Entrant Routing Lab • Cleanup Routing Lab (optional) • Floorplanner Lab (Area Based Floorplanning - optional) • EPIC Lab (Editing a Design / Adding a Probe Pin - optional) • Timing Improvement Lab • Guide Lab (optional) • Summary

49. Useful References • Refer to Chapter 12 (Attributes, Constraints and Carry Logic) of the Xilinx Libraries Guide for a full list of all supported constraints and examples of syntax • What else is new in M1.5/i ? Take a look at the Xilinx Implementation Tools Release 1.5 Features Application Note: • http://www.xilinx.com/apps/xactstep.htm • Support.xilinx.com • Troubleshoot - Answers Database • Software - Software Updates (patches) • Library - Expert Journals (ex - Timing Presentation)/ App Notes/ Software Manuals/ Tutorials