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PLL with VCO Band Selection Ko-Chi Kuo

PLL with VCO Band Selection Ko-Chi Kuo

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PLL with VCO Band Selection Ko-Chi Kuo

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  1. PLL with VCO Band SelectionKo-Chi Kuo

  2. Auto Band Selection Outline PART I: Concept Review • Auto Band Selection Concept • Auto Band Selection Interface with other Blocks(PLLs, VCOs, S.I. ) PART II: Circuit Design Review • Divide 8 and ECL to CMOS Circuit and Simulation • 9 Bit Programmable Counter and Simulation • Band Selection Interface Schematic and Simulation • Reset DFF Schematic and Simulation • VCO Phase Noise Simulation • Auto Band Selection Simulation • Summary

  3. PART I:Band Selection Concept Review PART I: Concept Review • Auto Band Selection Concept • Auto Band Selection Interface with other Blocks(PLLs, VCOs, S.I. )

  4. Auto Band Selection Concept • The need of Auto Band Selection • Multi-Band Solution Using CMOS Binary Digital Varactor • Frequency Coverage of RFVCO over 8 Bands • Requirements for Band Selection Algorithm to Work • How the Band Selection Works • Frequency Comparison Concept • Frequency Resolution with 8 Band RF VCO • Frequency Resolution with 4 Band IF VCO • Band Select Circuit Design • Band Select Circuit Timing Diagram • Summary

  5. 2.xxGHz 2.36GHz 60MHz: Minimum required coverage for WCDMA at any temperature 2.30GHz 2.yyGHz The need of Auto Band Selection • VCO frequency variations over temperature(2%) and process(%9) The minimum RF VCO Frequency Coverage(at RF LO)

  6. Multi-band Solution Using CMOS Binary Digital Varactor • Frequency Tuning is achieved through: • CMOS Binary Band-Select Capacitors • Small Integrated PIN Diode Varactor Frequency Total Frequency Coverage at given process and temp. Vtune

  7. Frequency Coverage of RF VCO over 8 Bands Desired Cover Range 4.6 –4.72 GHz (2.56%) Guard bands for process & temperature 5.4% each Band overage is 84%. The band coverage at (000) is 230 MHz for Core VCO, 115MHz after divide-by-2. * courtesy from Dawn Wang’s RFVCO CDR presentation.

  8. Requirements for Band Selection Algorithm to Work • Band Selection is performed each time a new channel is selected. • There is minimum overlap (f ) between two adjacent bands to cover the maximum expected temperature drift (+/-100 degree C) once a band is chosen. . . . . . . . . . Frequency (LO) Band=3 Band=2 • Given Minimum Band Overlap (Df) : 105MHz • 100degree (C) temperature drift: +/- 40MHz • BS Algorithm tolerance: +/- 4MHz • Vtune Bias Error: +/- 5MHz • Band separation Mismatch: This is accounted for in the Minimum Band Overlap (Df) • Df > 2 x (40M + 4M + 5M) = 98MHz Band=1 Band=0 Overlap: f 0.5 2.35 Vtune Band Switching Decision Point

  9. How the Band Selection Works . . . • At Power Up: • -- All registers set to zero (as default) • -- Vtune is set to 2.35V • Load (fLO (MHz) + 49) / 8 into Band Select Register thru Serial Interface. • -- This loading action triggers Band Select Algorithm • Compare Frequencies. • -- (fLO + 49MHz) / 8 > fVCO ? • Band selection counter (register) counts up as long as (fLO + 49MHz) / 8 > fVCO . • Freeze BS Counter when: • (fLO + 49MHz) / 8 < fVCO • Vtune voltage control is released. • * Above procedures are automatic except steps 1 and 2. . . . . . . Frequency (LO) Band=3 Band=2 Band=1 Band=0 Overlap: f 0.5 2.35 Vtune Band Switching Decision Point • Comparison at 2.35Volts reduces algorithm error caused by Vtune voltage variations and Overlap variations.

  10. RF_VCO ABS Interconnection Diagram & Operation Synthesizer RF_ABS 3bits BS<2:0> fREF BS_Man BS_Reset EN( BS Enable) fREF _Off Vtune 2.35V Vtune RBS<8:0> VCO_in 9bits • R-register of IF PLL is used to generate 1MHz f_REF for both RF and IF ABS circuits. • BS_Man overrides ABS algorithm and allows manual control of Band_Sel <2:0> • BS_Reset resets all the registers inside ABS circuit blocks.

  11. Down Counter reaches ‘0’ before next fREF ? Cnt_Start enabled at fREF ABS Operation Flowchart Start / Power Up Start Down Count As default: fREF = disabled Freeze = Low (Disabled) BS_Reset = Low BS_Man = Low Vtune = 2.35 Volts yes • Freeze goes High • fREF = Disable • Freeze BS<2:0> • Reset all other Reg’s to ‘0’ • Vtune_Release goes High Load R-Register of IF PLL thru SI to output 1MHz fLO is desired VCO frequency for IF and RF PLL • Increase BS<2:0> by one • Reload DN_Counter Load [ fLO(MHz) + 49] / 8 to RBS & IBS thru S.I. Vtune (VCO input) is reconnected to loop filter output for normal operation Loading RBS & IBS tirggers EN high – triggers BS operation Ready for normal operation of PLL • Reset BS <2:0> to zero • fREF is enabled From here on operation is synchronized to fREF END Load RBS (or IBS) value onto DN_Counter

  12. Frequency Resolution with8 Band RF VCO • The resolution of band selection counter is set to (fLO + 49MHz) / 8 so that difference between two band can be larger enough to chose the right band. In this case, each difference is about 3~4 clock cycles.

  13. Frequency Resolution with 4 Band IF VCO • Given Minimum Band Overlap (Df) : 82MHz • 100degree (C) temperature drift: +/- 26MHz • BS Algorithm tolerance: +/- 4MHz • Vtune Bias Error: +/- 4MHz • Band separation Mismatch: This is accounted for in the Minimum Band Overlap (Df) • Df > 2 x (26M + 4M + 4M) = 68MHz • The resolution of band selection counter is set to (fLO + 34MHz) / 8 so that difference between two band can be larger enough to chose the right band. In this case, each difference is about 4~8 clock cycles.

  14. 8 D D D D D D D Q Q Q Q Q Q Q Q Q Q Q Q Band Selection Circuit Design(RF) Load (fLO (MHz) + 49) / 8 every 1sec using : RBS register 2330MHz / 8 = 291MHz 9-bits BS_enable Vtune fVCO / 8 VCO Freeze 9-bit Down Cntr DN_Cnt Cntr = high ? EN Vtune_Release Reload Freeze_b EN Band_Sel<2:0> Freeze Decode_C EN fVCO / 8 TWIF_ENB Band_Sel <2:0> BS_enable BSR Freeze 3-bit FREF 3-bit Counter CNT_Start BS_Cnt RMB Reload Freeze fREF rst rst Reload DN_Cnt fREF EN BSR rst TWIF_Clk TWIF_ENB RMB BS_Man Freeze rst 2.35V BSR Vtune SWITCH LPF_out * Using Clk and En inputs of S.I. to manually control Band Selection * BSR, RBS and RMB are inputs from S.I. Freeze RMB * Vtune is determined by vtune release LPF_out is from off-chip LPF Vtune_Release

  15. 8 D D D D D D D Q Q Q Q Q Q Q Q Q Q Q Q Band Selection Circuit Design(IF) Load (fLO (MHz) + 34) / 8 every 1sec using : RBS register 1554MHz / 8 =194MHz Vtune 8-bits BS_enable fVCO / 8 VCO Freeze DN_Cnt 9-bit Down Cntr EN Cntr = high ? Vtune_Release Reload Band_Sel<2:0> Freeze_b EN Freeze Decode_C EN fVCO / 8 TWIF_ENB Band_Sel <1:0> BS_enable BSR Freeze 3-bit FREF 3-bit Counter CNT_Start BS_Cnt RMB Reload Freeze fREF rst rst Reload DN_Cnt fREF EN BSR rst TWIF_Clk TWIF_ENB IMB BS_Man Freeze rst BSR 2.35V Vtune SWITCH LPF_out * Using Clk and En inputs of S.I. to manually control Band Selection * BSR, RBS and IMB are inputs from S.I. Freeze IMB * Vtune is determined by vtune release LPF_out is from off-chip LPF Vtune_Release

  16. fREF EN BS_Enable Freeze Cnt_Start Reload Dn_Cnt BS_Cnt Band Selection Circuit Timing Diagram

  17. Summary of Auto Band Selection Algorithm • Band Selection is necessary for the RF and IF VCOs in order to overcome the VCO frequency drift due to the process and temperature variations. • The proposed Band Selection Algorithm takes 2sec per band and less than 20 sec(RF)/12 sec(IF) to accomplish Automatic Band Selection. • Frequency comparison is made through counting the frequency of fRF/8 signal during 1sec (all digital solution.) • Small overhead in silicon area and No Extra Current Consumption.

  18. PART I:Band Selection Concept Review PART I: Concept Review • Auto Band Selection Concept • Auto Band Selection Interface with other Blocks(PLLs, VCOs, S.I. )

  19. Auto Band Selection Interface with other Blocks(PLL, VCO, LPF, S.I.) • RF Top Schematic of ABS, PLL, VCO, LPF, and S.I. • IF Top Schematic of ABS, PLL, VCO, LPF, and S.I.

  20. RF TOP of ABS, PLL, VCO, LPF, S.I. RPC<8:0> TCXO Oscillator RSC<4:0> RRC<7:0> CPS<1:0> Data RPE Iout TWIF_Clk RCP RF Low Pass Filter LPF_out RF PLL Serial Interface TWIF_EN FREF (From IF PLL) SWITCH 2.35V vcon_rf RF Auto Band Selection Vtune vcop_rf RF VCO Vtune_release RVE Band_Sel<2:0> RBS<8:0> BSR RMB Decode_C

  21. IF TOP of ABS, PLL, VCO, LPF, S.I. IPC<8:0> TCXO Oscillator IRC<7:0> CPS<1:0> Data IPE Iout TWIF_Clk ICP IF Low Pass Filter LPF_out IF PLL Serial Interface TWIF_EN FREF (From IF PLL) SWITCH 2.35V vcon_if IF Auto Band Selection Vtune vcop_if IF VCO Vtune_release IVE Band_Sel<1:0> IBS<7:0> BSR IMB Decode_C

  22. PART II:Band Selection Circuit Design Review PART II: Circuit Design Review • Divide 8, Biasing, and CML to CMOS Circuit Schematic and Simulation • 9 Bit Programmable Counter Schematic and Simulation • Band Selection Interface Schematic and Simulation • Reset DFF Schematic and Simulation • VCO Phase Noise Simulation • Auto Band Selection Top Level Simulation • ABS, PLL, VCO, LPF Top Level Simulation • Summary

  23. Auto Band Selection: Divide 8, Biasing, CML to CMOS Circuits • Auto Band Selection: Divide 8, Biasing • Corner Simulation Condition • Circuit Simulation Result • Simulation Summary

  24. 8 Auto Band Selection: Divide 8 and Biasing RBS<8:0> (from S.I.) Control Signal (from S.I.) VCO_vtune (to VCO vtune) Vtune_release Band Selection Band_Sel<2:0> Auto Band Interface LPF_out 9-bit Down Cntr (from LPF) (to VCO Band select lines) PWD 3-bit Counter Vtune_release Vbias Control Logic Bias circuit FREF (From IF PLL) Reset Power on Reset circuit

  25. Auto Band Selection Divide 8 and CML to CMOS circuit Simulation Corner Frequency is set at 2.5GHz, Supply Voltage is 2.85V

  26. Auto Band Selection: Divide 8 and CML to CMOS circuit Simulation Result

  27. Auto Band Selection Divide 8 and CML to CMOS circuit Simulation Summary

  28. PART II: Circuit Design Review • Divide 8, Biasing, and CML to CMOS Circuit Schematic and Simulation • 9 Bit Programmable Counter Schematic and Simulation • Band Selection Interface Schematic and Simulation • Reset DFF Schematic and Simulation • VCO Phase Noise Simulation • Auto Band Selection Top Level Simulation • ABS, PLL, VCO, LPF Top Level Simulation • Summary

  29. Auto Band Selection: 9 Bit Programmable Counter • Auto Band Selection: 9 Bit Programmable Counter • Corner Simulation Condition • Circuit Simulation Result • Power down/up Simulation Result • Corner Simulation Result • Simulation Summary

  30. 8 Auto Band Selection: 9 Bit Programmable Counter RBS<8:0> (from S.I.) Control Signal (from S.I.) VCO_vtune (to VCO vtune) Vtune_release Band Selection Band_Sel<2:0> Auto Band Interface LPF_out 9-bit Down Cntr (from LPF) (to VCO Band select lines) PWD 3-bit Counter Vtune_release Vbias Control Logic Bias circuit FREF (From IF PLL) Reset Power on Reset circuit

  31. Auto Band Selection Circuit Design9 Bit Programmable Counter Simulation Corner Frequency is set at 2.5GHz, Supply Voltage is 2.85V

  32. Auto Band Selection 9 Bits CounterCorner Simulation Results

  33. Auto Band Selection 9 Bits Counter Simulation Summary

  34. PART II: Circuit Design Review • Divide 8, Biasing, and CML to CMOS Circuit Schematic and Simulation • 9 Bit Programmable Counter Schematic and Simulation • Band Selection Interface Schematic and Simulation • Reset DFF Schematic and Simulation • VCO Phase Noise Simulation • Auto Band Selection Top Level Simulation • ABS, PLL, VCO, LPF Top Level Simulation • Summary

  35. Auto Band Selection: Band Selection Interface • Auto Band Selection: Band Selection Interface • Auto Band Selection: Band Selection Interface Buffer Circuit worst case simulation • Auto Band Selection: Band Selection Interface Circuit Simulation Result • Auto Band Selection: Band Selection Interface with VCO, PLL, LPF Simulation Result • Simulation Summary

  36. 8 Auto Band Selection: Reference Clock Generator RBS<8:0> (from S.I.) Control Signal (from S.I.) VCO_vtune (to VCO vtune) Vtune_release Band Selection Band_Sel<2:0> Auto Band Interface LPF_out 9-bit Down Cntr (from LPF) (to VCO Band select lines) PWD Vbias 3-bit Counter Vtune_release Control Logic Bias circuit FREF (From IF PLL) Reset Power on Reset circuit

  37. Auto Band Selection Band Selection Buffer Worst Case Simulation

  38. Auto Band Selection Interface:Buffer AC Phase Margin Simulation AC open loop gain=70dB Phase Margin=60

  39. Auto Band Selection Interface:Buffer Step Input Response Simulation vout Settling time=200ns Step input

  40. Auto Band Selection Interface Simulation Result VCO_Vtune=2.35V (settled 300ns after power on) VCO_Vtune (goes to VCO) VCO_Vtune=LPF_in (after ABS find the right band) ABS find the right band and shut down the ABS PWD (generated by this interface) This is power on period Vtune_release Power_down LPF_in (comes from LPF)

  41. Auto Band Selection Interface with VCO, PLL, LPF Simulation Result LPF initial condition :0.5V VCO_Vtune Vtune_release

  42. Auto Band Selection Interface with VCO, PLL, LPF Simulation Result LPF initial condition :2.35V VCO_Vtune Vtune_release

  43. Auto Band Selection Interface Simulation Summary • The Interface circuit provides the VCO vtune voltage based on ABS status, one is a fixed 2.35V, the other source is from off-chip LPF output. • When ABS select the right band, it generates the power down signal to shut down the current of ABS circuit. • Simulation result shows that after interface circuit shut down ABS, PLL and VCO can still handle LPF initial condition.

  44. PART II: Circuit Design Review • Divide 8, Biasing, and CML to CMOS Circuit Schematic and Simulation • 9 Bit Programmable Counter Schematic and Simulation • Selection Interface Schematic and Simulation • Band Reset DFF Schematic and Simulation • VCO Phase Noise Simulation • Auto Band Selection Top Level Simulation • ABS, PLL, VCO, LPF Top Level Simulation • Summary

  45. Auto Band Selection: Band Power On Reset DFF Circuit • Auto Band Selection: Band Power On Reset DFF Circuit • Circuit Simulation Result

  46. 8 Auto Band Selection: Band Power On Reset DFF Circuit RBS<8:0> (from S.I.) Control Signal (from S.I.) VCO_vtune (to VCO vtune) Vtune_release Band Selection Band_Sel<2:0> Auto Band Interface LPF_out 9-bit Down Cntr (from LPF) (to VCO Band select lines) PWD Vbias 3-bit Counter Vtune_release Control Logic Bias circuit FREF (From IF PLL) Reset Power on Reset circuit

  47. Auto Band Selection Reset DFF Simulation Result Power On Reset Power On

  48. PART II: Circuit Design Review • Divide 8, Biasing, and CML to CMOS Circuit Schematic and Simulation • 9 Bit Programmable Counter Schematic and Simulation • Selection Interface Schematic and Simulation • Band Reset DFF Schematic and Simulation • VCO Phase Noise Simulation • Auto Band Selection Top Level Simulation • ABS, PLL, VCO, LPF Top Level Simulation • Summary

  49. Auto Band Selection: VCO and Switch Phase Noise Test • Circuit Simulation Result • Auto Band Selection: VCO and Switch (with divide 2) Phase Noise Test Bench • Circuit Simulation Result • Simulation Summary

  50. Auto Band Selection: VCO and Switch Phase Noise Test • Circuit Simulation Result • Circuit Simulation Result • Simulation Summary