Hardware/Software Integration in Portable Systems

1. Hardware/Software IntegrationinPortable Systems Trevor Pering University of California Berkeley

2. Outline This talk describes several research projects over the last six years that have relied heavily on integrated hardware/software design. • Background: The InfoPad Project • Energy Efficient Microprocessors • System Design Environment

3. InfoPad InfoPad InfoPad InfoPad Overview Internet • Perform all computation in the network tominimize client energy dissipation Wireless Basestation Compute Server CentralizedApplication Database High-bandwidth radio connection Workstation capabilities on a portable device!

4. InfoPad InfoPad Software Architecture Internet • Communicate through centralized server toprovide transparent ‘wired’ semantics Wireless Basestation “PadServer” SpeechRecognizer WebBrowser Transmit audio and raw bitmaps across the wireless link Example:Hand-heldspeech-enabled web-browser Maintain state in the network, not on the Pad

5. Main data-flow handled by custom low-power ASICs PacketHeader Frame- buffer update Control Statistics Reliability Debugging 10 MIPSμProcessor RX Packet Frame Buffer InfoPad Hardware Flexibility • Use hardware/software integration toprovide energy-efficient high-level functionality Embedded software responsible for high-level functions Only header sentto microprocessor Radio Entire packet routed to dedicated hardware

6. Intercom InfoPad InfoPad Evolution Total Power: ~7 W Where did the power go? • High-level system design optimizes complete solution and drives new research Inefficientimplementation Energy-EfficientProcessors Commercial DC/DC No local computation? Commercial radios

7. Outline • The InfoPad Project: • Energy-efficient integrated system design • Energy Efficient Microprocessors:Dynamic Voltage Scaling • System Design Environment

8. Dynamic Voltage Scaling (DVS) E  V2 • Trade-off energy and speed through voltage tominimize energy consumed fmax(V-c)/V E  fmax Energy ~Work • Speed

9. 10xenergysavings DVS vs. Fixed-Voltage • Reduce both speed and voltage tominimize both power and energy DVS: Voltage: 3xSpeed: 10xEnergy: 10xPower: 100x

10. SRAM SRAM SRAM Intercom DVS Project Charter Scale voltage of entire microprocessor system! • Design microprocessor system tosupport low-power devices Dynamic Voltage Regulator lpARM lpARM General-purpose software controls system voltage I/O I/O operations independent of processor architecture

11. DVS Scheduling Framework Energy ~ Work • Speed • Use real-time framework toconstrain task voltage scheduling Start Deadline Start Deadline Lower speed,Lower voltage, Lower energy Idle time represents wasted energy µProc. Speed Work Work Time

12. S1 S2 S3 D2 D3 D1 µProc. Speed W1 W2 W3 W1 Time DVS Scheduling Task runs faster to meet timing constraints • Schedule all tasks so as to minimize system energy dissipation Similar to minimizing xi2 with constant xi

13. D3 S1 S2 S3 D1 D2 Speed Intercom Time DVS Simulation • Simulate run-time scheduler tofully understand voltage-scaling behavior Interrupts Cache Behavior Task Variance Scheduling Overhead User Input Weather Implementation Theory Reality

14. SPEC Intercom Simulation Benchmarks • Model accurate I/O interaction toevaluate effects of voltage scaling • Audio Decryption • Graphical UI • MPEG Decode • Run-Time Support

15. Simulation Infrastructure GUI MPEG { Frame_Start(deadline); Decode_MPEG_Frame(); Frame_Finish(); } • Develop support environment tomodel complete software system Cryptography Windowing VoltageScheduler I/O Support MPEG  Priority 80 GUI  Priority 23 Applicationsupport libraries lpARM Run-time Scheduler Speed Priority

16. Simulation Run-Time Algorithm Schedule all tasks as if they were currently runnable: O(n3) • Relax scheduling constraints toschedule efficiently in real-time O(n log n) Present time S1 S2 S3 D2 D3 D1 Speed = Work / Time µProc. Speed W2 W3 W1 Time Execute W1 because W2 is not yet runnable

17. Run-Time Scheduling Dynamics Run faster to make up lost time Thread accomplishing more than expected,reduce speed • Periodically re-evaluate schedule toadjust for unforeseen events Deadline exceeded,increase speed Higher-priority task µProc. Speed Optimal schedule E(work) Initial speed estimate Time Workload calculated to be average of previous frames

18. SystemIdle Voltage Scheduler MPEGDecoder InterruptHandler μProcessor Speed Run-Time Execution Trace Frame Deadlines • Simulate the entire system tomeasure overhead and effectiveness SchedulingOverhead < 3% Time

19. Results: Run-Time Voltage Scaling Normalized to 3.3V fixed-voltage processor • Dynamic Voltage Scalingsignificantly reduces energy dissipation! Includes 10% DVS implementation overhead Combination of independent benchmarks

20. Run-Time Performance Analysis • Application characteristics strongly affectvoltage scaling performance 0 2x deadline Audio MPEG GUI Software can automatically recognize and adjust forbi-modal GUI distribution Normalized to deadline at max processor speed

21. Disk DSP CPU mem D3 S1 S2 S3 D1 D2 Speed Intercom Time * + Beyond Dynamic Voltage Scaling • Voltage scheduling framework can be applied to many different designs and technologies lpARM DSP

22. Outline • The InfoPad Project: • Energy-efficient integrated system design • Dynamic Voltage Scaling: • Software control to minimize energy • System Design Environment:Top-Down Microprocessor Design

23. Dynamic Voltage Regulator lpARM SRAM SRAM SRAM I/O The lpARM Project Control & Software Processor validation & optimization Trevor Pering • Combine diverse backgrounds todevelop an energy-efficient microprocessor Dynamic Voltage Regulator Processor Design 0.6 m DVS ARM8 processor with 16 kB on-chip cache Speed: 10 - 100 MHz Voltage: 1.1 - 3.3 V Energy: 0.18 - 2.2 nJ/cycle Power: 1.8 - 220 mW Tony Stratakos Tom Burd Silicon expected May 1999

24. Intercom lpARM Top-Down Design Functional Specification • Use top-down design flow to optimize and verify design =? ANSI CFunctionalSimulation Cycle-levelInstruction Simulation Iterative design lpARM VHDL/LayoutHardware Simulation

25. System Simulation lpARM Feature Specification Scale voltage tominimize energy • Simulate high-level system todiscover desired implementation features • Energy-saving processor features: • Dynamic speed control • Execution cycle counter • Low-power sleep mode • Interrupt speed control • … Functional Specification

26. lpARM End-to-End Verification Functional Specification Functional Simulation • Compare inter-simulation results toverify end-to-end design Frame 1 Chk: 0x2dbf92c2 Frame 2 Chk: 0x32fe4cda Frame 3 Chk: 0x3aa0d4ac Frame 4 Chk: 0x93efa7c8 Frame 5 Chk: 0x28f4efa9 Application-level frame checksum Instruction Simulation =? SRAM Memory hierarchy coherency lpARM VHDL Simulation Strict cycle-level comparison lpARM TransistorSimulation

27. lpARM Application Evaluation Intra-groupnormalized to 32-CAM • Evaluate target applications toaccurately represent system behavior Direct-mapped cache is very application sensitive ‘DVS energy’ includes system performance

28. lpARM System-Level Optimization • Evaluate the complete system early-on todirect architectural design • Other parameters analyzed: • Write-back/Write-through • Allocation policy • Write-buffer size • Associativity

29. Control & Software D3 S1 S2 S3 D1 D2 Voltage Regulator Processor Design Speed Intercom Time lpARM Design Summary Top-down • Simulating top-down hardware/software design improves end result Scale voltage to minimize energy Hardware and software componentscombine to form a system solution lpARM

30. Conclusion • The InfoPad Project • Energy-efficient integrated system design • Dynamic Voltage Scaling • Software control to minimize energy • Top-Down Microprocessor Design • Application-driven energy optimization Effective energy-efficient systems requirecomplete top-to-bottom integrated design