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Lesson 4: “Just like LEGO”

Lesson 4: “Just like LEGO”. The NAND gate “Reading” CMOS gates Designing CMOS gates. Logic. NAND 2-inputs. “Gates are inverters in disguise!”. NAND 3-inputs. NAND 3-inputs. NAND: Switching Time, Propagation Delay. t Low2High = R p /N (N*C out , p +C out , n /N+C load )

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Lesson 4: “Just like LEGO”

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  1. Lesson 4: “Just like LEGO” The NAND gate “Reading” CMOS gates Designing CMOS gates

  2. Logic

  3. NAND 2-inputs “Gates areinverters in disguise!” Gates

  4. NAND 3-inputs Gates

  5. NAND 3-inputs Gates

  6. NAND: Switching Time, Propagation Delay tLow2High= Rp/N (N*Cout,p+Cout,n/N+Cload) tHigh2Low= N*Rn (Cout,n/N+N*Cout,p+Cload) Gate Delay=1/2*(tL2H+ tH2L) n,p : n-channel, p-channel transistors. Rp,Rn: Ron of respective transistors. N = number of Inputs.

  7. Estimation of Gate Delay: Gate Delay = K1(pSec) +K2 (pSec*um/fF)* Cload / WnWn=Width of n-channel FET (Wp/Wn=constant)K1 & K2 determined from spice simulation of cascaded inverters. Wp/Wn K1 K2 1 39 12.8 2 38 8.78 3 41 6.35 When FETs in series, the effective W is respectively smaller. Cload calculated from Fan-out * Capacity(per Gate) + Capacity of Line.

  8. NAND 3-inputs Gates

  9. NAND 3-inputs Gates

  10. “Reading” CMOS gates Gates

  11. Designing CMOS gates Gates

  12. Complex CMOS gates • Can a compound gate be arbitrarily complex? • NO, propagation delay is a strong function of fan-in: • FO  Fan-out, number of loads connected to the gate: • 2 gate capacitances per FO + interconnect • FI  Fan-in, Number of inputs in the gate: • Quadratic dependency on FI due to: • Resistance increase • Capacitance increase • Avoid large FI gates (Typically FI  4) Gates

  13. NAND: Switching PointVSP=(bn / (N*bp))^1/2*VT,n+(VDD-VT,p) --------------------------------------1+(bn / (N*bp))^1/2N = number of Inputs.n,p : n-channel, p-channel transistors.

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