Experience with the design and submission of the Medipix3 pixel readout chip in 0.13 µm CMOS

1. Experience with the design and submission of the Medipix3 pixel readout chip in 0.13 µm CMOS X. Llopart RD51 Paris-14th October

2. Outline • Introduction to the Medipix3 • Medipix3 prototype • Medipix3 requirements • Available tools • IP Blocks • Through Via Silicon • Verification • Conclusions

3. Performance of the Medipix2 & Timepix • Single photon counting provides excellent noise free images • Ideal in photon starved situations • Many different application both foreseen and otherwise! • Electron microscopy for biology • Neutron imaging • Nuclear power plant decommissioning • Adaptive optics for astronomy • Dosimetry in space • Gas detectors • www.cern.ch/Medipix X-ray transmission image of a termite worker body (left) and detail of its head (bottom). Even the fine internal structure of the antennae is recognized. (Magnified 15x, time=30 s, tube at 40 kV and 70 mA)

4. Introduction to Medipix3 • Main limitations of the Medipix2 chip: • Charge sharing in the sensor is an issue: • Flat field correction is sensitive to incoming spectrum • Threshold should be exactly half of peak for correct counting with monochromatic illumination • Energy resolution is limited by charge sharing tail • Detector is ‘blind’ during readout (only one counter per pixel) • Using serial readout it takes about 5ms to read out one frame • Only 3-side buttable • Radiation hardness • The Medipix3 collaboration started on June 2005 with 15 members (now 17) • By the end of 2005 a Medipix3 prototype with 8x8 55µm pixels was sent to fabrication

5. Medipix3 Prototype (R. Ballabriga) • IBM 130nm CMOS8RF with 8 metals LM process. MPW through MOSIS. • First tests around March 2006. • We tested the idea of local communication between 2x2 pixel clusters to correct the charge sharing distortion effect • It took ~1 year to fully test the prototype • We learned a lot from this step: • Gain mismatch between channels • Digital coupling into analog sensitive lines (arbiter signals-common summing node) • Signals producing double counting close to threshold • R. Ballabriga, et al. “The Medipix3 Prototype, a Pixel Readout Chip Working in Single Photon Counting Mode with Improved Spectrometric Performance”, IEEE Trans. Nucl. Sci., vol 54, pp: 1824 - 1829 • Prototyping is a time consuming but useful process!!! 1000 µm 2000 µm

6. Collaboration approved floorplan & requirements • Highly configurable pixels: • Maintain pixel and matrix size • Single Pixel Mode (SPM) • Charge Summing Mode (CSM) • Colour Mode (110 µm x 110 µm) • 2 independent thresholds per pixel (8 in colour mode) • 2 programmable counters with overflow (1, 4 or 12 bits) or 1-24 bit • Sequential Read/Write mode • Semi-Sequential Read/Write mode • Continuous Read/Write mode • Pixel counter fast Reset • Maximize active area: • Multiple-dicing options and minimal IO periphery • Through Via Silicon pads (TVS) included on-chip • Increase connectivity flexibility: • Region (Block) of interest readout • Minimize number of lines • All control/data lines use LVDS • Configurable data output port (1 to 8) • On-chip Band-Gap and DACs • On-chip test pulse • E-fuses for chip identification

7. Which tools we had • IBM CMOS8RF 130 nm → Technology has many possibilities (manual of 520 pages…): • Thin (2.2 nm) and thick (5.2 nm) gate oxide NFET/PFET • Low power (high threshold) or Regular (low threshold) NFET/PFET • Zero-VT thin and thick NFETs • Thin Triple Well NFETs • 3.3V IO NFET/PFET • 5 to 8 metal layers of different “flavours” (LM, MA and OL) with Cu and Al. • MIM capacitors (only in MA and OL) • E-Fuses • And more… • Digital design flow using ARM/Artisan standard cells and IO pads • Design flow was realized by Manhattan Routing tuned for an LM process. • New verification tools (ASSURA, CALIBRE) matched with the IBM design kit

8. The right choice of technology “flavour” • IBM CMOS8RF 8-metals with MA was chosen: • Good: • We needed MIM capacitors at the shaper front-end. This would free quite some area. • Smaller inter-layer capacitances -> Smaller input capacitance ! • Top metal is already thick Al which is needed for bump-bonding • M7 is thick Cu -> Good power distribution • Bad: • Prototype was done in 8-LM -> Re-check simulations • Our digital design flow (MRE) was based in a LM BEOL • Devices used: • Pixel: • Regular thin NFET/PFET (Analog) • MIM capacitors (Analog) • Low power thin NFET/PFET (Digital) • Periphery: • Regular thin NFET/PFET (core logic) • Regular thick NFET/PFET (IOs) • Zero-Vt thick NFET (LVDS driver) • 3.3V IO NFET/PFET (e-fuse) • E-fuses

9. Pixel schematic

10. Pixel layout 55 µm • Full custom design -> 3 man-years (Rafa and Winnie) • Basic matrix cell is a 2 x 2 pixel matrix • Each pixel contains ~1600 trts: > 100 Mtrts • Changes from the prototype: • Some enclose layout NFETs for radiation tolerance enhancement • Added MIM caps • Programmable binary counter (1, 4, 12 or 24 bits) with overflow • Fast matrix Reset • 13 configuration bits per pixel • 2 independent test pulse circuits per pixel column • Two power domains: • AVDD 1.5 V: 10.1 µA/pixel max • VDD 1.5 V: 10 nA/MHz/pixel -> 2 µA/pixel @ 200 MHz readout clock) 55 µm

11. Medipix3 Periphery (I) • 1 man-year (Xavi) • All the data communication is done through the bottom periphery. • Chip needs between 12 (1 data out port) to 18 (8 data out ports) LVDS pairs. • 1 analog output line is use to monitor the internal DACs • 4 different power domains • This block has been synthesized and automatically laid out using the digital design flow from MRE EoC 253 EoC 0 TpC 0 TpC 2 TpC 253 EoC 254 TpC 254 EoC 255 TpC 255 EoC1 TpC 1 EoC 2 IO Logic E-Fuses (32 bits) Band-Gap and 25 DACs DataIn AVDD, VDD, DVDD25 and AVDD33 ClkIn EnableIn Reset Shutter Shutter1 FastClear Shutter1 TP_Switch DataOut0 DataOut1 DataOut2 DataOut3 DataOut4 DataOut5 DataOut6 DataOut7 EnableOut ClkOut x8 in Ext BG Ext DAC x10 out DACOut

12. Medipix3 Periphery (II) • Several blocks have been full custom designed and then integrated inside the digital flow: • LVDS driver (VDD/DVDD) • LVDS receiver (VDD/DVDD) • E-fuses block (VDD/AVDD33) • Analog Periphery (Band-Gap, 25 DACs and monitoring logic) (AVDD) • End Of Column (VDD) • Test Pulse circuitry (AVDD) • The periphery has been synthesized using a target readout clock frequency of 350 MHz • The design has been verified at this frequency with the post-layout realization with parasitic RC

13. LVDS 130nm Tx & Rx • Medipix3 will use only LVDS for the chip IO communication • 8 Receivers: Reset, Shutter, Shutter1_CounterSelCRW, MatrixFastClear, TP_Switch, EnableIn, ClockIn, DataIn. • 10 Drivers: EnableOut, ClockOut, DataOut[0..7] • No LVDS drivers available in the IBM CMOS8 ARM IO libraries → Must be designed in-house (full-custom) • Requirements: • ~500 Mbps • Minimum power consumption • Dual power (VDDio: 2.5V and VDDcore: 1.2-1.5V): Use of thick and thin oxide FET !!! • Radiation Hard: ELT for the Thick oxide NFETs (New extraction tool for ASSURA LVS is available) • Must be included in the standard CMOS8 ARM IO MA pad size for compatibility with the digital design flow (73 x 247 µm)

14. LVDS Driver • Based in the 0.25 µm LVDS driver from Paulo Moreira (CERN) • Added auto-bias circuitry • Monte-Carlo simulation with Process and Mismatch corners and (RLC wire bond parasitics) and VDDcore=1.5V @ 500 MHz • Radiation hard

15. LVDS Receiver • Based on a schematic from Miguel Novais (CERN) for a 1.2Gbit/s receiver. • Self-biased (always on) • Radiation hard

16. LVDS Layout • Layout fits in the ARM IO library pitchsize • 2 PBAREWIRE cells side by side which were emptied. Only ESD diodes were kept. • Both cells have been digitally characterized and included in the digital design flow. • All thick oxide NFETs have been laid out as ELTs LVDS_RX LVDS_TX 247µm 146µm

17. E-Fuses • IBM stop providing the laser blown fuses: “The “laser fuses” cost more, occupy more area than the e-FUSE, function at the wafer level only, and prohibit placement of circuits below and wiring above the fuse”. • E-fuses are made by electronically “burning” a salicidedpolysilicon strip. Before and after burning the resistance is changed from ~100 Ω to >5KΩ • This means: • Wafers from IBM will come “blank” • Higher system complexity : logic to burn and logic to read • Burning needs 3.3V power supply • Programming transistor current Ion 10 mA < Ion < 13.5mA • Programming time: > 0.18 ms and < 1.0 ms • 32-bit included and burned during probe testing

18. E-Fuse block layout • Programming: • Programming pulse length (> 0.18 ms and < 1.0 ms) is set by a 9-bit register. • Fuse selection for programming is done through a 5-bit fuse decoder. Only 1 bit burned at a time. • Reading: • All e-fuses read at once • MC simulations shows a sense threshold of 500Ω ±100 Ω 14µm 30µm 65µm 300µm

19. Analog periphery: Band-Gap • Medipix3 includes a band-gap voltage reference (designed and tested by P. Moreira) • The forward voltage of one of the band-gap diodes is used to monitor the temperature • Power supply sensitivity: 1.2 mV/VAVDD • Temperature sensitivity: 0.1 mV/ºC • The output of the band-gap is use for the on-chip DACs to generate their output with minimal temperature and power supply dependence 235µm 1000µm

20. Analog periphery: DACs • There are 25 DACs on-chip: 10 x 9-bits and 15 x 8-bits DACs • 18 linear current and 7 linear voltage output DACs • Power supply sensitivity: 1 LSB per 250 mVAVDD • Temperature sensitivity: 1 LSB per 25 ºC • Transistor current matching in 0.13 µm is ~2 times worst than in 0.25 µm -> bigger transistors for the same current copy. Why? Different substrate resistivity! 235µm 235µm 230µm 450µm

21. End Of Column 22 µm • There is 1 End of Column cell per column realized with the MRE flow • It includes column buffering and CTPR and DACs registers • Cell has been tested on all corners successfully up to 750 MHz • Medipix2/TimepixEndOfColumn + buffering was ~200 µm x 34 µm (75% bigger) • Propagation delay <3ns from bottom to top of the column (using metal with of 400 nm and total line capacitance of 3pF) 68.4 µm <3ns <3ns

22. On-chip test pulse • There are 2 independent test pulse circuits per column in order to test the charge summing circuitry (TP_1 and TP_2) • The test pulse amplitude range is controlled by 3 voltage DACs (TP_REFA, TP_REFB and TP_REF) • The test pulse frequency is controlled by LVDS input TP_SWITCH

23. Medipix3 Periphery • IO Logic • Includes ~1nF on-chip decoupling capacitance between VDD and VSS • Synthesized using MR • Powered through VDD/VSS • E-fuses • 32-bits • Enclosed NMOS transistors used for improved radiation hardness. • Powered through VDDA33/VDDA/VSSA • EoColumn and TPulse buffer • 1 EoC per column (VDD/VSS) • 2 TpC per column (VDDA/VSSA) • BG and DACs (25) • BG from P.Moreira with temperature sensor • 10 9-bit DACs and 15 8-bit DACs • Powered through VDDA/VSSA • IO pads • ARM power pads used • LVDS IN/OUT and SenseOut pads use enclosed NMOS transistors used for improved radiation hardness. • All pads include TVS connection • DVDD/DVSS VDD/VSS VDDA/VSSA

24. IO Pads strategy TSV M1 TSV M1 70µm • The IO power pads used are from the GPIO MA CM0S8 ARM library • This library includes full ESD protection circuitry • Two types of bonding possible: • Wire bonding (WB) • Through Silicon Via (TSV) IBMIO 130nm IBMIO 130nm IBMIO 130nm IBMIO 130nm 247µm WB WB WB WB 1000µm WB WB WB WB 247µm 73µm

25. Bottom left corner • The center of the first active pixel is at 1804 µm with WB extensions or at 804 µm with TV. • Row of sensor guard-ring connected to VSSA. • Alignment marks in the four corners of the chip. • Through via High-Voltage pads in the four corners of the chip. • Logo details: 800µm 1000µm

26. Through Via Silicon (TSV) • Through Silicon Via (TVS) technology is a vertical electrical connection passing completely through a silicon wafer or die. • The connection to the PCB is then done through BGA -> Dead area due to WB is eliminated ! • Typical state of the art TSVs in a 50 µm thinned wafer are 35 µm diameter vias with a 60 µm minimum pitch. Timepix to BGA using TSV (Z. Vykydal)

27. Medipix3 TVS landing pads • The TVS landing pads are laid out in M1 with an octagonal shape of 70 µm diameter. • There are 108 in-line TVS pads at the bottom and 84 in-line TVS pads at the top. • There are 4 rectangular TVS for the High Voltage connection to the back of the detector either via BB or WB. 70µm 78µm 135µm

28. 14100 µm 14100 µm 14100 µm 14100 µm 14100 µm Medipix3 chip • Top Metal (MA) and passivation opening (DV) displayed • Multiple dicing cuts depending on: • Top power connection • WB or TSV bonding 14900 µm 15900 µm 15300 µm 17300 µm 17300 µm

29. Medipix3 DRC • CALIBRE DRCTM used • Many DRC errors still present due to: • ZVT enclosed layout gates in LVDS tx • Mim cap area -> Vmax ≥ 6V • MQ to gate RX diode per pixel (GR131f) • Bump bonding openings in the pixel • Multi-dice options • These DRC errors were sent to IBM for waiver clearance • Answer from IBM : “the design can be manufactured but CERN accepts entirely the risks involved by violating the specific design rule”

30. Medipix3 LVS • CALIBRE (from Mentor Graphics) was used for the first time in the group for doing LVS inside Cadence -> lots of manual reading! • This is a true hierarchical tool. ASSURA? • Final LVS run for ~10h in a 8 core CPU with 16 GB. Chip completed !!!

31. Conclusion • The Medipix3 chip is the first 130 nm engineering run organized through the CERN HEP service. • The Medipix3 prototype demonstrated the principle of local communication between pixels to solve charge sharing effects. • From there still took 4 man-years (3 people) for the completion of the design. Why? • Change of BEOL technology from the prototype • New programmable counter • Many unavailable blocks (DACs, LVDS driver and receiver, e-fuse bits, …) • Use new tools for the first time (MRE, CALIBRE LVS, …) • Experience gained should reduce design time for future projects • Chip was sent to IBM 24th September !!!