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Online testing of Complex VLSI circuits using FDD Theory of Discrete Event System

Online testing of Complex VLSI circuits using FDD Theory of Discrete Event System . Principal Investigator : Dr. Santosh Biswas Co Investigator: Dr. J.K. Deka , Prof. S. Nandi. Objective of the Project.

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Online testing of Complex VLSI circuits using FDD Theory of Discrete Event System

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  1. Online testing of Complex VLSI circuits using FDD Theory of Discrete Event System Principal Investigator : Dr. Santosh Biswas Co Investigator: Dr. J.K. Deka , Prof. S. Nandi

  2. Objective of the Project • Adaptation of Failure Detection and Diagnosis (FDD) technique of Discrete Event system (DES) for On-line testing (OLT) of Complex VLSI Circuits • Development of CAD tools to facilitate design of complex VLSI circuits with OLT capabilities • Setup of a Digital VLSI test facility • Validation using FPGA based platform using the test facility

  3. The basic aim of the project is to adapt the DES based OLT scheme for complex circuits. The adaptations required are the following DES modeling of the circuits at higher abstraction level compared to gate level e.g., RTL (register transfer level), Core level (for interconnects), System C, C++ Fault modeling at higher level of abstractions and correlation with accepted fault models like stuck-at, bridging, delay etc. Tradeoff analysis at higher level of abstractions

  4. OVERVIEW Step 1 Step 2 Create a Project in Xilinx ISE Get the Technology Schematic (.ngc) Extract LUT information from the edif file Convert .ngc file format to EDIF file format Step 3 Step 4 Gives the required Gate-level information (.pla) Provide LUT information to the tool Final output Step 5

  5. Step 1: Creating a Project in Xilinx ISE Verilog Code here generates a full adder and two multiplexers and are used to show 3 types of LUT(Look Up Table) configuration. LUTs can be of 2, 3, 4 input configuration with 1 output. • Open XILINX ISE • Create a project • Write code in Verilog language

  6. Step 2: Synthesized the code to get Technology Schematic view Technology schematic view information is stored in a file with file extension .ngc In the diagram, q, rst, x, y, z are inputs and out, out1, out2, out3 FIGURE: Technology Schematic view

  7. In the diagram, there are four LUTS. • LUT4_4114 • LUT4_5440 • LUT2_8 • LUT3_FE • LUT4 refers that there are 4 inputs to the LUT. Similarly, LUT2 and LUT3 refers there are 2 and 3 inputs the LUTs respectively. FIGURE: Inside view of the TECHNOLOGY Schematic

  8. The Initials of the LUTs’ i.e. 4114, 5440, 8 and FE are the values that we get from the truth table for the respective LUTs. Taking the example of LUT4_4114 Output (O) is read from bottom of the table. That means first 4 comes for the combination. 1100 0 1101 0 1110 1 1111 0 We have to note that XILINX student edition does not provide any Gate-Level information unlike Cadence. TABLE NO. 1: TRUTH-TABLE OF LUT4_4114

  9. Step 3: Convert .ngc file format to edif file format • STEPS TO GENERATE EDIF FILE • Open command prompt • Change directories and go to the folder where the ngc file is present. • Write the following code as shown in the screenshot below and press enter. FIGURE : COMMAND PROMPT VIEW TO MAKE EDIF FILE FROM NGC FILE

  10. Step 4 EDIF file of the above example EXTRACTED LUT INFORMATION FROM EDIF FILE #LUTSTART out21 LUT2 8 #LUTEND #LUTSTART out31 LUT3 FE #LUTEND #LUTSTART mux_carry-mux_out1 LUT4 5440 #LUTEND #LUTSTART mux_sum-mux_out1 LUT4 4114 #LUTEND (edif main (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0)) (status (external UNISIMS (edifLevel 0) (technology (numberDefinition)) (cell LUT2 (cellType GENERIC) (view view_1 (viewType NETLIST) (interface (port I0 (direction INPUT) ) (port I1 (direction INPUT) ) (port O (direction OUTPUT) ) (instance out21 (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) (property XSTLIB (boolean (true)) (owner "Xilinx")) (property INIT (string "8") (owner "Xilinx")) ) (instance out31 (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) (property XSTLIB (boolean (true)) (owner "Xilinx")) (property INIT (string "FE") (owner "Xilinx")) From this file, we have to extract the information which are being highlighted.

  11. Step 5: Provide LUT information to the Tool The file containing LUT information is processed through our tool to generate Gate-Level information. The Gate-level information is stored in files with “pla” format. • The steps to generate pla file are shown below: • Open command prompt. • Run the tool with EDF file name as argument • PLA files will be created inside “output” sub-directory of the current path FIGURE : SCREENSHOT 1 FIGURE : SCREENSHOT 2

  12. Final Gate-Level information file with .pla file extension #.model mux_sum-mux_out1 .i 4 .o 1 .ilb I0 I1 I2 I3 .ob O0 .p 4 0011 1 0101 1 1001 1 1111 1 .e #.model out21 .i 2 .o 1 .ilb I0 I1 .ob O0 .p 1 11 1 .e #.model out31 .i 3 .o 1 .ilb I0 I1 I2 .ob O0 .p 7 001 1 010 1 011 1 100 1 101 1 110 1 111 1 .e #.model mux_carry-mux_out1 .i 4 .o 1 .ilb I0 I1 I2 I3 .ob O0 .p 4 0111 1 1011 1 1101 1 1111 1 .e

  13. Objective achieved • From Xilinx ISE we have extracted the gate level information from a RTL circuit using our own tool. • Xilinx ISE is a free tool. • The softwares like Synopsys and Cadence have the in built facility for the gate level netlist but the disadvantage is the cost of these softwares are very high.

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