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EE365 Adv. Digital Circuit Design Clarkson University Lecture #4 Transistor Level Logic CMOS vs. TTL

EE365 Adv. Digital Circuit Design Clarkson University Lecture #4 Transistor Level Logic CMOS vs. TTL. Topics. CMOS Logic Devices Bipolar Logic Devices. Lect #4. Rissacher EE365. MOS Transistors. Voltage-controlled resistance. PMOS. NMOS. Lect #4. Rissacher EE365. Switch Model.

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EE365 Adv. Digital Circuit Design Clarkson University Lecture #4 Transistor Level Logic CMOS vs. TTL

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  1. EE365 Adv. Digital Circuit Design Clarkson University Lecture #4 Transistor Level Logic CMOS vs. TTL

  2. Topics • CMOS Logic Devices • Bipolar Logic Devices Lect #4 Rissacher EE365

  3. MOS Transistors Voltage-controlled resistance PMOS NMOS Lect #4 Rissacher EE365

  4. Switch Model Lect #4 Rissacher EE365

  5. CMOS Inverter Lect #4 Rissacher EE365

  6. Alternate transistor symbols Lect #4 Rissacher EE365

  7. CMOS Gate Characteristics • No DC current flow into MOS gate terminal • However gate has capacitance ==> current required for switching (CV2f power) • No current in output structure, except during switching • Both transistors partially on • Power consumption related to frequency • Slow input-signal rise times ==> more power • Symmetric output structure ==> equally strong drive in LOW and HIGH states Lect #4 Rissacher EE365

  8. CMOS Gate Operation • Java applet showing CMOS gates • visit: tech-www.informatik.uni-hamburg.de/applets/cmos/ • illustrates gate operation, including power drain during switching • Link is on class website Lect #4 Rissacher EE365

  9. output A Pull-down B C GND Pull-up / Pull-down Model • Typical CMOS gate can be viewed as consisting of two parts • pull-up network and pull-down network VDD A Pull-up B C Lect #4 Rissacher EE365

  10. Pull-up / Pull-down Model • High level inputs to the PDN cause switches to close • If there is a closed switch path thru PDN, then output is low • Low level inputs to the PUN cause switches to close • If there is a closed switch path thru PUN, then output is high Lect #4 Rissacher EE365

  11. output A Pull-down B C GND Pull-up / Pull-down Model Since hign level signals on the inputs cause the PDN to close switches, we get a Boolean expression for the input which creates a closed path thru PDN A A and ( B or C) B C If a closed path exists in PDN, then the output is pulled low. Thus the logic function realized is the complement (inverted) version of the Boolean expression. not (A and ( B or C)) Lect #4 Rissacher EE365

  12. Pull-up / Pull-down Model What happens when the Boolean expression is false? Since there is no path thru PDN, the output could float. In order to make the output high, the PUN must have a path which connects VDD to the output. Observe: take the expression for PDN and use DeMorgans Law to write it in terms of complemented input variables. Complemented variables are true when the input level is low. Thus, this gives exactly the form of the PUN In this case: not A or ( not B and not C) Lect #4 Rissacher EE365

  13. CMOS NAND Gates • Use 2n transistors for n-input gate Lect #4 Rissacher EE365

  14. CMOS NAND -- switch model Lect #4 Rissacher EE365

  15. CMOS NAND -- more inputs (3) Lect #4 Rissacher EE365

  16. CMOS – non-inverting buffer Lect #4 Rissacher EE365

  17. CMOS – 2-input AND gate • Note the number of transistors compared to NAND (6 vs. 4) Lect #4 Rissacher EE365

  18. In-Class Practice Problem • Design a CMOS NOR circuit • Hint: Like NAND shown earlier, NOR circuits have 2n transistors for n-input gate (this one has 4) Lect #4 Rissacher EE365

  19. CMOS NOR Gates • Like NAND -- 2n transistors for n-input gate Lect #4 Rissacher EE365

  20. NAND NOR NAND vs. NOR • NMOS has lower “on” resistance than PMOS (important when multiple transistors are in series) • Result: NAND gates are preferred in CMOS due to speed Lect #4 Rissacher EE365

  21. Cascade Structure for Large Inputs • 8-input CMOS NAND Lect #4 Rissacher EE365

  22. Complex Logic Functions • CMOS AND-OR-INVERT gate Lect #4 Rissacher EE365

  23. Tri-State • We lied - “binary” outputs have more than two values • Some gates are designed to have a third value - a high impedance • Effectively disconnects the gate output from the circuit Lect #4 Rissacher EE365

  24. Tri-State Application Lect #4 Rissacher EE365

  25. Open Drain • Device without the internal active pull-up network on the output • Why ? • Allows for two or more outputs to be connected together • Produces a “wired” AND function • Requires a pull-up resistor Lect #4 Rissacher EE365

  26. Open Drain Application Lect #4 Rissacher EE365

  27. CMOS Families • 4000 series - mostly obsolete • HC • HCT (input levels compatible with TTL) • AC • ACT (input levels compatible with TTL) • FCT and FCT-T (both TTL compatible) Lect #4 Rissacher EE365

  28. Bipolar Logic Families Lect #4 Rissacher EE365

  29. TTL Digital Circuits • Designed using “transistor-transistor logic” (remember EE341 ?) • npn bipolar junction transistors • Transistors operate in either • cut-off mode • no base current => no collector current • saturated mode • base current pulls VCE to ~ 0.2 v Lect #4 Rissacher EE365

  30. A Simplified TTL NAND Gate Lect #4 Rissacher EE365

  31. Schottky Transistors • Addition of Schottky diodes between base and collector prevent saturation • Schottky diode has lower forward bias voltage drop (0.25 v). • Resulting design is called a Schottky transistor • Speeds switching time by reducing charge storage in saturation Lect #4 Rissacher EE365

  32. TTL NAND Gate Lect #4 Rissacher EE365

  33. Special TTL outputs • Standard output stage is called “totem pole” output • Tri-state outputs • Open collector (or CMOS open drain) • requires external pull-up resistor • allows wired-AND function Lect #4 Rissacher EE365

  34. TTL differences from CMOS • Asymmetric input and output characteristics. • Inputs source significant current in the LOW state, leakage current in the HIGH state. • Output can handle much more current in the LOW state (saturated transistor). • Output can source only limited current in the HIGH state (resistor plus partially-on transistor). • TTL has difficulty driving “pure” CMOS inputs because VOH = 2.4 V (except “T” CMOS). Lect #4 Rissacher EE365

  35. TTL Families • 7400 series (5400 “mil spec”) • 74 S - Schottky • 74 LS - low power Schottky • 74 AS - advanced Schottky • 74 ALS - advanced low power Schottky • 74 F - Fast TTL Lect #4 Rissacher EE365

  36. TI’s Logic Products Lect #4 Rissacher EE365

  37. TTL (S, LS, AL, ALS, F) 5 v 0 v Comparison of Signal Levels CMOS (HC, AC) CMOS (HCT, ACT) 5 v 5 v VOH 4.4 v VIH 3.5 v VOH 2.4 v VOH 2.4 v VIH VIH 2.0 v 2.0 v VIL 1.5 v 0.8 v 0.8 v VIL VIL 0.5 v 0.4 v VOL 0.4 v VOL VOL 0 v 0 v Lect #4 Rissacher EE365

  38. Another Practice Problem • Attempt to draw a truth table for the following circuit. Hint: List each transistor in the truth table and show whether it is on of off for each input combination A B C D Lect #4 Rissacher EE365

  39. Another Practice Problem • OR-AND-INVERT Z H H H H H L L L H L L L H L L L Lect #4 Rissacher EE365

  40. Next Classes • Memorial Day – NO CLASS ! • Tues. - Help Day for Project # • Wed. – Class Postponed • Thur. - Electrical Behavior, Power & Timing

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