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EE365 Adv. Digital Circuit Design Clarkson University Lecture #12 Registers and Counters

EE365 Adv. Digital Circuit Design Clarkson University Lecture #12 Registers and Counters. Topics. Registers Counters. Lect #12. Rissacher EE365. Multibit registers and latches. 74x175. Lect #12. Rissacher EE365. 8-bit (octal) register. 74x374 3-state output. Lect #12.

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EE365 Adv. Digital Circuit Design Clarkson University Lecture #12 Registers and Counters

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  1. EE365 Adv. Digital Circuit Design Clarkson University Lecture #12 Registers and Counters

  2. Topics • Registers • Counters Lect #12 Rissacher EE365

  3. Multibit registers and latches • 74x175 Lect #12 Rissacher EE365

  4. 8-bit (octal) register • 74x374 • 3-state output Lect #12 Rissacher EE365

  5. Other octal registers • 74x273 • asynchronous clear • Non-three state output • 74x377 • clock enable • no tristate-buffer Lect #12 Rissacher EE365

  6. Octal latch • 74x373 • Output enable • Latch-enable input “C” or “G” • Register vs. latch, what’s the difference? • Register: edge-triggered behavior • Latch: output follows input when G is asserted Lect #12 Rissacher EE365

  7. EN EN EN EN EN RESET EN EN EN EN EN EN EN EN Counters • Any sequential circuit whose state diagram is a single cycle. Lect #12 Rissacher EE365

  8. Lect #12 Rissacher EE365

  9. LSB Serial enable logic MSB Synchronous counter Lect #12 Rissacher EE365

  10. LSB Parallel enable logic MSB Synchronous counter Lect #12 Rissacher EE365

  11. 74x163 MSI 4-bit counter Lect #12 Rissacher EE365

  12. 74x163 internal logic diagram • XOR gates embody the “T” function • Mux-like structure for loading Lect #12 Rissacher EE365

  13. Counter operation • Free-running 16 • Count if ENP andENT both asserted. • Load if LD is asserted(overrides counting). • Clear if CLR is asserted (overrides loading and counting). • All operations take place on rising CLK edge. • RCO is asserted if ENT is asserted andCount = 15. Lect #12 Rissacher EE365

  14. Free-running 4-bit ’163 counter • “divide-by-16” counter Lect #12 Rissacher EE365

  15. Modified counting sequence • Load 0101 (5) after Count = 15 • 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 5, 6, … • “divide-by-11” counter Lect #12 Rissacher EE365

  16. trick to save gate inputs Another way • Clear after Count = 1010 (10) • 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2, 3, … • “modulo-11” or “divide-by-11” counter Lect #12 Rissacher EE365

  17. Counting from 3 to 12 Lect #12 Rissacher EE365

  18. Cascading counters • RCO (ripple carry out) is asserted in state 15, if ENT is asserted. Lect #12 Rissacher EE365

  19. Decoding binary-counter states Lect #12 Rissacher EE365

  20. Decoder waveforms • Glitches may or may not be a concern. Lect #12 Rissacher EE365

  21. Glitch-free outputs • Registered outputs delayed by one clock tick. • We’ll show another way to get the same outputs later, using a shift register. Lect #12 Rissacher EE365

  22. Shift registers • For handling serial data, such as RS-232 and modem transmission and reception, Ethernet links, etc. • Serial-in, serial-out Lect #12 Rissacher EE365

  23. Serial-to-parallel conversion • Use a serial-in, parallel-out shift register Lect #12 Rissacher EE365

  24. mux Parallel-to-serial conversion • Use parallel-in, serial-out shift register Lect #12 Rissacher EE365

  25. Do both • Parallel-in, parallel-out shift register Lect #12 Rissacher EE365

  26. “Universal” shift register74x194 • Shift left • Shift right • Load • Hold Lect #12 Rissacher EE365

  27. One stage of ’194 Lect #12 Rissacher EE365

  28. Shift-register counters • Ring counter Lect #12 Rissacher EE365

  29. Johnson counter • “Twisted ring” counter Lect #12 Rissacher EE365

  30. LFSR counters • Pseudo-random number generator • 2n - 1 states before repeating • Same circuits used in CRC error checking in Ethernet networks, etc. Lect #12 Rissacher EE365

  31. Next time • More Serial • Clock Skew • Synchronization Lect #12 Rissacher EE365

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