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Lecture on :- ARITHMATIC OPERATIONS By – GURJIT SINGH SRS GPCG , Ludhiana

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Lecture on :- ARITHMATIC OPERATIONS By – GURJIT SINGH SRS GPCG , Ludhiana.

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Lecture on :-ARITHMATIC OPERATIONSBy – GURJIT SINGHSRS GPCG , Ludhiana

INTRODUCTIONArithmetic Instructions in digital computers manipulate data to produce results necessary for the of activity solution of computational problems. These instructions perform arithmetic calculations and are responsible for the bulk of activity involved in processing data in a computer. The four basic arithmatic operations are addition,subtracton,multiplication,division. From these basic operations, it is possible to formulate other arithmatic functions and solve scientific problems by means of numerical analysis methods . An arithmetic processor is the part of a pro cessor unit that execute arithmatic operations .

The data type assumed to residein prosser registers during the execution of an arithmetic instructions is specified in the definition of the instruction . An arithmetic instructions may specify binary or decimal data, and in each case the data may be in fixed point or floating-point form . Fixed-point numbers may represent integer or fractions. Negative numbers may be in signed – magnitude or signed – complement representation. The arithmetic processor is very simple if only a binary fixed-point add instructons is included. It would be more complicated if it includes all four arithmetic operations for binary and decimal data in fixed-point and floating – point representation.

“The solution to any problem that is stated by a finite number of well defined procedural steps is called algorithm. ”

The four basic arithmetic operations are

- ADDITION
- SUBTRACTION
- MULTIPLICATION
- DIVISION

ADDITION AND SUBTRACTION

There are three ways of representing negative fixed point binary numbers :

- Signed Magnitude
- Signed 1’s complement
- Signed 2’s complement

Most computer use the signed 2’s compliment representation when performing arithmetic operations with integers . For floating point operations , most computers use the signed magnitude representation.

ADDITION AND SUBTRACTION WITH SIGNED MAGNITUDE DATA

The representation of numbers in signed magnitude is familer because it is used in everyday arithmetic calculations . the procedure for adding or subtracting to signed binary numbers with paper and pencil is simple and straight forword . a review of this procedure will be helpful for deriving the hardware algorithm.

We designate the magnitude of two numbers by A and B . When the signed numbers added and subtracted , We find that there are eight different conditions to concider , depending on the sign of the numbers and the operations performed. This conditions are listed in the first coloum of table . The others coloum in the table show the actual operations to perform with the magnitude of numbers .

The last coloum Is needed to prevent a negative zero. In other words , when two equals numbers are subtracted , the result should be + 0 and – 0 . The algorithm for addition subtraction are derived from the table and can be stated as follows.

Examples

Example of adding two magnitudes when the result is the sign of both operands:

+3 0 011

+ +2 0 010

+5 0 101

-3 1 011

+ +2 0 010 -( +3 011

- +2) 010

- 1 1 001

Example of adding two magnitudes when the result is the sign of the larger magnitude:

Addition Algorithm:

When the signs of A and B are identical. Add the two magnitude and attach the sign of A to the result . When the signs of A and B are different , compare the magnitude and subtract the smaller numbers from the larger .

Choose the sign of the result to be the same as A if A > B or compliment of sign of A if A < B .If the two magnitude are equal , subtract B from a and make the sign of the result positive. The two algorithms are similar except for the sign comparrision . The procedure to be followed for identical signs in the addition algorithm is the same as for different sign in the subtraction algorithm and vice versa.

HARDWARE IMPLEMENTATION

- To implement the two arithmetic operation with hardware , it is first necessary that the two numbers be stored in registers. Let A and b to registers that hold the magnitude of the numbers , and As and Bs be two flip – flop that hold the corresponding sings . the result of the operation may be transferred to a third registers : however , a saving Is achived if the result is transferred Into A and As . Thus A and As together form and accumulator registers . Consider now the hardware implementation of the algorithm above . first, a parallel – adder is needed to perform the mirooperation A + B . second , comparator circuit is needed to establish if A>B, X=B, A<B. Third , two parallel-subtractor needed to perform the microoperations A – B and B – A . The sign relationship can be determined from an excellucive and OR gate with As and Bs as inputs . This procedure requires a magnitude comparator , addeFirst , we know that

require less r and two subtractor . however a different procedure can be less equipment. foundFirst we know that subtraction can be accomplished by mean of compliment and add . Second thee result of a compresion can be determined for the end carry after the subtraction . Carefull investigation of alternatives reveals that the use of 2’s compliment for subtraction and compression is an efficent procedure that require only an adder and a complementer. Fig . show a block diagram of hardware for implementing the addition and subtraction operation, It consist of registers A and B sign flip – flops As and Bs. Subtraction is done by adding A to the 2,s complement of B

The output carry is transferred to flip-flop E , where it can be checked to determined the relative magnitude of two numbers.

Addition and Subtraction with Signed-Magnitude Data Hardware Design

B register

Bs

Mode Control

Complementer

AVF

M

Parallel Adder

E

Input Carry

Output Carry

S

A register

As

Load Sum

The add overflow flip-flop AVF hold the overflow bit when A and B are added . The A register provide other micro-operation that may be needed when we Specify the sequence of steps in algorithm. The addition of A + B is done through the parallel adder. The S (sum) of adder is applied to input of A register . The complimenter provides an output of B or compliment of B depending on the state of mode control M . The complimenter consist of Excellusve – OR gate and the parallel adder consist of full-adder circuit as shown in figure. The M signal is also applied to the input carry is 0 . and the output of the adder is equal to sum A+B. When M = 1 ,The 1’s complement of B is appilied to the adder , the input carry is 1 , and output S=A+b+1 . this is equal to A plus the 2’s ompliment of b , which is equelevent to the subtraction , A – B.

Hardware algorithm

The two signs As and Bs are compared by an exclusive –OR gate . If the output of the gate is 0,the signs are identical; if it is 1 ,the signs are different. For an add operation, identical signs dictate that magnitudes be added. For a subtract operation, different s detcates that the magnitudes be added . The magnitudes are added with a microoperationigns EA A+B where EA is a register that combines E and A. The carry in E after the addition constitutes an overflow if it is equal to1. The value of E is transferred into the add-overflow flip –flop AVF.The two magnitudes are subtracted if the signs are different for an add operation or identical for a subtract operation. The magnitudes are subtracted by adding A to operation or identical for a subtract operation . The magnitudes are subtracted by adding a to the 2’s complement of B

. No over flow can occur if the numbers are subtracted so AVF is cleared to 0.a 1 in indicates that A>B and the number in A is the correct result.If this number is zero,the sign As must be made positive to avoid a negative 0. A0 in E indicates that A<B . For this it is necessary to take the 2’s compliment of the value os A . This operation can be done with one micro-operation . In other paths of the flowcharts,the sign of the result is the same as the sign of A,so no change in As is required. However,when A<B, the sign of the result is the complement of the original sign of A.It is necessary to complement As to obtain the correct sign.The final reslut is found in register A and it sign in As. The value in AVF provides an overflow indication.The final value of E is inmaterial.

ADDITION AND SUBTRACTION WITH SIGNED 2’S COMPLEMENT DATA

The left most bit of a binary number presents sign bit : 0 for +ve and 1 for –ve . If the sign bit is 1,the entire number is represented in 2’s compliment form thus, + 33 is represented by 00100001 and -33 by 11011111which is 2’s compliment of 00100001 and vice versa.

The addition of two number in signed-2,s compliment from consist of adding the numbers with the sign bit treated the other bits of the numbers . A carry – out of the sign –bit position is discarded .The consist of first taking the 2’scompliment of the subtrahend and then adding it to the minuend. When two numbers ofndegits each are added and the sum occupies n+1 digits, we say that an overflow can be dedicated by inspecting the last two carries out of the addition . when the two carries are applied to an exclucive- or gate , the out of the addition . When the two carries are applied to an exclusive - Or gate , overflow is detected when the output of the gate is equal to 1. The register configuration for the hardware implementation is shown in figure . This is the same configuration as in fig except that the sign bits are not seprated . From the rest of the registrators. We name the A register AC (accumulator) and the B register BR .

The leftmost bit in AC and BR represent the sign bits of the numbers . The two sign bits are added or subtracted together with the other bits in the complementer and parallel added . The overflow flip-flop V is set to 1 if tjere is an overflow . the outout carry in this case is discarded . The algorithm for adding and subtracting two binary numbers is signed 2’s complement representation is shown in the flow chart. The sum of obtained by adding the contents of AC ad BR . The over flow bit V is a set to 1 if the exclusive-OR of the last two carries in 1 , and it is cleared to 0 otherwise . The subtraction operation is accomplished by addibg the content of AC to the 2’s compliment of BR . Taking the 2’s compliment of BR has the effect of changing is +ve number to –ve , and vice versa. An overflow must be checked during this operation because the two numbers added could have the sane sign. The programmer must realize that if an overflow occur , there will be an erroneous results in the AC register.

Comparing these algorithm with its signed magnitude counterpart, we note that it is much simpler to add an subtract numbers if –ve numbers are maintained in signed – 2’s compliment representation. For this reason most computers adopt this representation over the more familer signed magnitude .

MULTIPLICATION ALGORITHMS

Multiplication of two fixed point binary numbers in signed magnitude representation is done with paper and pencil by a process of successive shift adds operations. This process is best illustrated with a numerical example . the process consist of looking at successive bits of the multiplier , least significant bit first . If the multiplier bit is a 1 . the multiplicand is coppied down ; otherwise , zero’s are copied down . the number copied down in successive lines are shifted one position to the left from the previous number . Finally ,the numbers are added their sum forms are product.

23 10111 Multiplicand 19x 10011 Multiplier

10111

10111

00000 +

00000

10111

437 110110101 Product

Hardware implementation for Signed magnitude data

When multiplication is implemented in a digital computer,it is convinent to change the process slightly. First,instead of providing register to store and add simuntaneously as many binary numbers as there are bits in the multiplier,it is convenient to provide an adder for the summation of only two binary numbers and succesfully accumulate the partial products in a register . Second ,instead of shifting the multiplicant to the left ,the partial product is shifted to the right,which results in leaving the partial product and multi plicant in the required relative

positions.Third,when the corresponding bit of the multiplier is zero,there is no need to add all zeros to the partial product since it will not alter its value.The hardware for multiplication consists of the equipment shown in fig plus two more registers.These registers together with registers A and B are shown in the fig.The multiplier is stored in the Q register and its sign in Qs.The sequence counter SC is initially set to a number equalt to the number of bits in a multiplier. The counter is decremented by 1. After forming each partial product. When the content of the counter reaches 0,the product is formed and the process is stop. Initially,the multiplicant is in register B and the multiplier in Q.

The sum of A and B forms a partial product which is tranferred to the EA register. Both partial product and multiplier are shifted to the right. This shift will denoted by the statement shr EAQ to designate the right shift depicted in fig.The least significant bit of A is shifted into the most significant position of Q,the bit form E is shifted into the most significant position of A, and 0 is shifted into E.After the shift ,one bit of the partial product is shifted into Q,pushing the multiplier bit one position to the right.

In this manner,the right most flip flop in register Q,designated by Qn will hold the bit of the multiplier, which must be inspected next.

Hardware algorithm

Figure is a flowchart of the hardware multiplying algorithm.Initially,the multiplicant is in B and the multiplier in Q. This corresponding sides are in Bs and Qs respectively

The signs are compared,and the both A and Q are set to correspond to the sign of product since a double length product will be stored in resistance A and Q.Registers A and E are cleared and the sequence counter SC is set,to a number equal to the number of the bitmultiplier. We are assuming here that operands are transfer to registers from a memory unit that has words of n bits.

since an operand must be stored with its sign,1 bit of the word will be occupy by the sign and the magnitude will consist of n-1 bits.

After the initialisation ,the lower order bit of the mutiplier in Qn is tested. If it is a 1,the multiplicant in B is added to the present partial product in B .If it is the 0,nothing is done.Register EAQ is then shifted once to the right to form the new partial product. The sequence cunter is decrementd by 1 and its new value is checked. If it is not equal to 0,the process is repeated and a new partial product is formed. The process stops when SC =0. Not that the partial product formed in Ais shifted into Q one bit at a time and eventually replace the multiplier . The final product is available in both A and Q, with A holding the most significant bits and Q holding the least significant bits.

The previous numerical example is repeated in table to clearify the hardware multiplication process. The procedures follow the steps outline in the flowchart

Hardware implementation for signed magnitude data:-

When the division is implemented in a digital computer,it is convenient to change the process lightly.

Instead of shifting the divisor to the right , the divident,or partial remainder,is shifted to the left, thus leaving the two numbers in required the relative position. Subtraction may be achieved by adding A to the 2’s complement of B. The information about the relative magnitudes is then available from the end –carry.

The hardware for implementing the division operation is identical to that required for multiplication and consists of the component shown in fig. Registers EAQ is now shifted to the left with 0 inserted into Qn and the previous value of E is lost . The numerical example is repeated in fig to clerify the propose division process.

The divisior is stored in the B register and the double length divident is stored in registers A ans Q. The divident is shifted to the left and the divisior is subtracted by adding its 2’s complement value. The information about the relative magnitude is available in E.

- IF E=1,it signifies the A>B. A quotient bit 1 is inserted into Qn and the partial reminder is shifted to the left to repeat the process. If E=0,it signifies that B>A.so the quotient in Qn remains a 0.The value of B is then added to restore the partial reminder in A to its previous value.
- The partial reminder is shifted to the left and the process is repeated again until all five quotient bits are formed. Note that while the partial remainder is shifted left, the quotient bits are shifted alos and alter five shifts, the quotients is in Q and the final remainder is in A. before showing the algorithm in flowchart form, we have to consider the sign of the result and a possible overflow condition.

The sign of the quotient Is determined form the signs of the dividend and the divisior. If the two signs are alike,the sign of the quotient is plus. If they are unlike.the sign is minus. The sign of the remainder is the same as the sign of the dividend.

BOOTH MULTIPLICATION ALGORITHM

- Booth algorithm gives a procedure of multiplying binary integer in signed 2’s complement representation. It operates on the fact that strig of 0’s in the multiplier require no addition but just shifting , and a string of 1’s in the multiplier from bit weight 2k to weight 2m can be treated as 2k +1 -2m . for example : the binary number 0011110 (+14) has a string of 1’s from 23 to 21 (k=3 , m=1)
- The number can be represented as
- 2 k + 1 – 2 m = 24 – 21 = 16 – 2 = 14

Booth algorithm requires examination of the multiplier bits and shifting of the partial products. Prior to the shifting ,the multiplicand may be added to the partial product , subtracted from the partial product , or left unchanged according to the following rules :-

- The multiplicand is subtracted from the partial product upon encountering the first least significant 1 in a string og 1,s in the multiplier.
- The multiplicand is added to partial product encountering the first 0 in string of 0’s in multiplier.
- The partial product does not change when the multiplier bit is identicial to the previous multiplier bit.

DIVISION ALGORITHM

Division of two fixed-point binary numbers is signed – magnitude representation is done with paper and pencil by a process of successive compare , shift, subtract operations . Binary divisionsis simpiler than decimal division because the quotient degit are either 0 or 1 and there is no need to estimate how many time the dividend or partial remainders fits into the divisor . The division is simpler then decimal division because the quotient degit are either 0 or 1 and there is no need to estimate how many times the dividend or partial remainders fits into the divisor . the division processs is illustrated by a numerical example :-

Divide overflow:-

- The division operation may result in a quotient with an overflow. This is not a problem when working with paper and pencil but is critical when the operation is implemented with hardware. This is because the length of registers is finite and willnot hold a number that exceeds the standard length. To see this, consider a system that has 5 bit registers. We use one register to hold the divisor and two registers to hold the dividend. From the example: The quotient is to be stored in a standard 5 bit register. This divide overflow condition must be avoided in normal computer operations because the entire quotient will be too long for transfer into a memory unit that has words of standard length that is same as the length of registers.Provision to ensure that this condition is detected must be included in either the hardware and software of the computer , or in a combination of the two . When the dividend is twice as long as the divisor , the condition for overflow can be stated as follows:

A divideoverflow condition occur if the high-order half bits of the dividend constitute a number greater than or equal to the devisor.

Another problem associated with division is the fact that a division by zero must be avoided. The divide overflow condition take care of this condition as well .This occur because any dividend will be greater than or equal to a devisor which is equal to zero. Overflow condition is usually detected when a special flip flop is set . We will call it a divide overflow flip-flop and label it DVF. The occurrence of a devide overflow can be handled in a varity of ways .In some computers it is the responsiblty of the programmer to check id DVF is set after each devide instruction. They then can branch to a subroutine that takes a corrective measure such as rescaling the data to avoid to overflow. In some older computers ,the occurrence of a divide overflow stopped the computer and this condition was referred to as a divide stop. Stopping the operation , of the computer is not recommended because it is time consuming .

The procedure in most computers to provide an interrupt request when DVF is set . The interrupt cases the computers to suspend the current program and branch to a service routine to take a corrective measure. The most corrective measure is to remove the program and type an error message explaining the reason why the program could not be completed. It is then the responciblity of the user who wrote the program to rescale the data or take any other corrective measure. The best way to avoid a divide overflow is to use floating point data .

Hardware algorithm:-

The hardware divide algorithm is shown in the flowchart of fig. the dividend is in A and Q and the divisor in B. The sign of the result is transferred into Qs to be part of the quotient. A constan6 is set into the sequence counter SC to specify the number of bits in the quotient . As in multiplication, we assume that operands are transferred to registers form a memory unit that has words of n bits . Since an operand must be stord in with its sign ,one bit of the word will be occupied by the sign and the magnitude will consist of n-1 bits . A divide-overflow condition is tested by subtracting or divisor in B from half of the bits of the dividend stored in A. If A >B the divideoverflow flip flop DVF is set and the operation is terminated prematurely .

If A<B , no divide overflow occur so the value of the dividend is stored by adding B to A . The division of the magnitude start by shifting into E . If the bit shifted into E is 1 , we know that EA >B because EA consists of a 1 followed by n-1 bits . In this case , B must be subtracted from EA and 1 inserted into Qn of the quotient bit . Since register A is missing the high-order bit of the dividend , its value is EA – 2n-1. Adding to this value the 2’s compliment of B result in :

(EA – 2n-1) + ( 2n-1-B) =EA - B

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