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ETRAX CRIS architecture and Xilinx FPGA. Peter Zumbruch Experiment control systems group GSI (KS/EE). Embedded Target Platforms ETRAX CRIS Xilinx FPGA - Virtex4/5 Summary. Overview . Aiming at two architectures ETRAX based CRIS architecture HADControl (aka: HADSHOPOMO) TRBv2

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etrax cris architecture and xilinx fpga

ETRAX CRIS architecture andXilinx FPGA

Peter Zumbruch

Experiment control systems group GSI

(KS/EE)

overview
Embedded Target Platforms

ETRAX CRIS

Xilinx FPGA - Virtex4/5

Summary

Overview

ETRAX CRIS architecture / Xilinx FPGA – Peter Zumbruch, GSI

epics embedded
Aiming at two architectures

ETRAX based CRIS architecture

HADControl (aka: HADSHOPOMO)

TRBv2

Experiments: HADES, CBM, Panda, …

Xilinx FGPA: Virtex 4 (5)

SysCore based Boards

Experiment(s): CBM, …

EPICS embedded

ETRAX CRIS architecture / Xilinx FPGA – Peter Zumbruch, GSI

hadcontrol based on etrax 100lx mcm by axis
HADControl based on ETRAX 100LX MCM by AXIS

Development of GSI’s Experimental Digital Electronic group (M.Traxler)

HADControl (aka HADSHOPOMO (HADES SHOWER POWER MONITOR) )

“Multi-purpose control/monitor device developed for HADES […] is based on the ETRAX 100LX MCM4+16 and runs the "Experimental Physics and Industrial Control System, EPICS”.

http://developer.axis.com/showroom

ETRAX CRIS architecture / Xilinx FPGA – Peter Zumbruch, GSI

trbv2 multi purpose daq board based on etrax fs by axis

Current Applications:

HADES complete DAQ upgrade, PET Readout Coimbra, PANDA, KVI,…

TRBv2 (multi purpose DAQ board)based on ETRAX FS by AXIS

http://www-linux.gsi.de/~traxler/GSIScientificReport2006_TRB/TRBv2_2006.pdf

ETRAX CRIS architecture / Xilinx FPGA – EPICS-Shanghai, SSRF - Peter Zumbruch, GSI

embedded epics on etrax
install embedded Linux on ETRAX chip CPU (axis.com) based front-end systems

2 step approach:

Install DIM on ETRAX and use EPICS-DIM Interface to communicate via network with external EPICS clients or IOCs

Suitable for development:

DIM protocol also accessible via other controls software, i.e. LabVIEW, or CS, etc.

But locally no (EPICS) logic (database, (fast) sequencing, alarming) provided

Embedded EPICS on ETRAX

CS

ETRAX CRIS architecture / Xilinx FPGA – Peter Zumbruch, GSI

what is dim
“DIM is a communication system for distributed / mixed environments.

It provides a network transparent inter-process communication layer.”

Protocol

Distributed Information Management System

Originally built for DELPHI

http://dim.web.cern.ch/dim/

Some Properties:

name based publisher/subscriber mechanism for services and commands

Small / Tiny

Many platforms

No (not yet) inherent access security

No logic

Dynamic

Used as network protocol for LabVIEW based CS Control system (GSI)

… another Gateway to LabVIEW

What is DIM?

ETRAX CRIS architecture / Xilinx FPGA – Peter Zumbruch, GSI

embedded epics on etrax1
install embedded Linux on ETRAX chip CPU (axis.com) based front-end systems

2 step approach:

Install DIM on ETRAX and use EPICS-DIM Interface to communicate via network with external EPICS clients or IOCs

Suitable for development:

DIM protocol also accessible via other controls software, i.e. LabVIEW, or CS, etc.

But locally no (EPICS) logic (database, (fast) sequencing, alarming) provided

Install EPICS Embedded on ETRAX

Provides all features of EPICS

Local fast EPICS based logic, network independent

By „turning the direction of the interface“ users may still see a DIM device, mimicked by EPICS using the EPICS – DIM interface

Embedded EPICS on ETRAX

CS

ETRAX CRIS architecture / Xilinx FPGA – Peter Zumbruch, GSI

etrax applications
HADControl Board (ETRAX 100LX MCM – linux-cris_v10)

Temperature Sensor 1-Wire Bus

Drift chamber HV-Interlock Control

development: CAN-Bus Controller

TRB (ETRAX FS – linux-cris_v32)

Resistive Plate Counter – Threshold settings via SPI protocol

Development: DAQ monitoring, FEE controls

ETRAX Applications

ETRAX CRIS architecture / Xilinx FPGA – Peter Zumbruch, GSI

epics on xilinx virtex4 5
Basis

Environment Platform (KIP (University of Heidelberg)) providing several soft cores (PPC/MicroBlaze)

with Linux (up-to-know µClinux) on it.

based on VMware image, ready to use

EPICS on Xilinx Virtex4/5

ETRAX CRIS architecture / Xilinx FPGA – Peter Zumbruch, GSI

outlook on epics on xilinx virtex4 5
Future Milestones

Software milestones

Implementation of gnu ppc cross compiler into EPICS build system (preferred)

or implement EPICS IOC build into Xilinx Build Process

or build EPICS on FPGA running gcc/make/perl on front-end

Hardware milestones:

Xilinx Evaluation Board ml403

Soft IOC

Soft IOC with Inter-process communication Run-Control

Nxyter / SysCore based board

DAQ Board (CBM)

Soft IOC (incl. IPC)

IOC with access to “external” Hardware on-Board

Configuration of Setups via EPICS

Outlook on EPICS on Xilinx Virtex4/5

ETRAX CRIS architecture / Xilinx FPGA – Peter Zumbruch, GSI

summary
Axis’ ETRAX

EPICS on ETRAX’ cris architecture

Connection to EPICS via ‘2 step approach’

ETRAX-DIM – EPICS-DIM-Interface – EPICS

also suitable for other architectures (i.e. XYZ-DIM – EPICS)

Outlook on Xilinx’ Virtex4/5

Different software solutions

Hardware

ml403

Nxyter / SysCore

Summary

http://wiki.gsi.de/Epics

ETRAX CRIS architecture / Xilinx FPGA – Peter Zumbruch, GSI

slide13

Thank you for your attention.

ETRAX CRIS architecture / Xilinx FPGA – Peter Zumbruch, GSI

epics dim interface
Implementation as “device support module”

Running

DIM SERVER

Providing read/write access to EPICS variables

DIM CLIENT

Interfacing DIM services and commands for single variables to EPICS process variables

Successfully used for 5 weeks continous HADES beam time

On demand

String transport mode (DIM provides strings converted by the Interface to single data types, easier to handle by EPICS)

Array and structures support

More EPICS records

EPICS

DIM

(protocol)

Client

EPICS-DIM

Interface

Device

Server

EPICS DIM Interface

ETRAX CRIS architecture / Xilinx FPGA – Peter Zumbruch, GSI