Design and Implementation of VLSI Systems (EN0160) Lecture 18: Static Combinational Circuit Design (2/2)

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Design and Implementation of VLSI Systems (EN0160) Lecture 18: Static Combinational Circuit Design (2/2) . Prof. Sherief Reda Division of Engineering, Brown University Spring 2007. [sources: Weste/Addison Wesley – Rabaey/Pearson]. Conversion of AND/OR circuits to NAND/NOR/INV circuits.

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## Design and Implementation of VLSI Systems (EN0160) Lecture 18: Static Combinational Circuit Design (2/2)

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Design and Implementation of VLSI Systems

(EN0160)

Lecture 18: Static Combinational Circuit Design (2/2)

Prof. Sherief Reda

Division of Engineering, Brown University

Spring 2007

Conversion of AND/OR circuits to NAND/NOR/INV circuits.

An asymmetric gate favor one input over the other(s).

A skewed gate favor one transition over the other(s).

Last lecture
We have selected P/N ratio for unit rise and fall resistance (m = 2-3 for an inverter).

Alternative: choose ratio for least average delay

• By sacrificing rise delay, pMOS transistors can be downsized to reduced input capacitance, average delay, and total area
What is the P/N ratio that gives the least delay?
pMOS is the enemy!

High input and diffusion capacitance for a given current

Can we take the pMOS capacitance off the input?

Various circuit families try to do this…

pMOS is the enemy!
Let’s get rid of pMOS
• Reduced the capacitance and improved the delay
• Increased static power consumption

How can we implement the R easily in a CMOS process?

[see subsection 2.5.4]

1. Pseudo-nMOS circuits
• In the old days, nMOS processes had no pMOS
• Instead, use pull-up transistor that is always ON
• In CMOS, use a pMOS that is always ON
• Ratio issue
• Make pMOS about ¼ effective strength of pulldown network

[see subsection 2.5.4]

pMOS fights nMOS

Logical effort of pseudo-nMOS gates

logical effort independent of number of inputs!

Pseudo-nMOS draws power whenever Y = 0

Called static power P = I•VDD

A few mA / gate * 1M gates would be a problem

This is why nMOS went extinct!

Use pseudo-nMOS sparingly for wide NORs

Turn off pMOS when not in use

Pseudo-nMOS power
Ganged CMOS

• When A=B=0:
• both pMOS turn on in parallel pulling the output high fast
• When both inputs are ‘1’:
• both pMOS transistors turn off saving power over psuedo-nMOS
• When one is ‘1’ or one is ‘0’ then it is just like the pseudo-nMOS case
Seeks the performance of pseudo-nMOS without the static power consumption2. Cascode Voltage Switch Logic (CVSL)
• Require input complement
• NAND gate structures can be tall and slow
3. Pass Transistor Logic
• just uses two transistors
• Problem:
• ‘1’ is not passed perfectly
• cannot the output to the input of another gate

A

Pass-Transistor

A

F

Network

B

B

(a)

A

Inverse

A

F

Pass-Transistor

B

Network

B

B

B

B

B

B

B

A

A

A

B

F=AB

A

B

F=A

ÅB

F=A+B

(b)

A

A

A

B

F

=

AB

A

F

=

A

ÅB

F

=

A+B

B

EXOR/NEXOR

AND/NAND

OR/NOR

Complementary Pass Transistor Logic (CPTL)
• Complementary data inputs and outputs are available
• Very suitable for XOR realization (compare to traditional CMOS)
• Interconnect overhead to route the signal and its complement

3.0

In

Out

V

2.0

[V]

DD

x

e

V

g

DD

Level Restorer

a

t

l

o

M

V

r

1.0

B

M

2

X

M

A

0.0

Out

n

0

0.5

1

1.5

2

Time [ns]

M

1

A better design: full swing; reduces static power

Possible solution: interface to a CMOS inverter

Threshold voltage loss causes static power consumption

(AKA Lean Integration with Pass Transistors - LEAP)

In pass-transistor circuits, inputs are also applied to the source/drain terminals.

Circuits are built using transmission gates.

Pass Transistor Logic with transmission gates
• Problem:
• Non-restoring logic.