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Reducing Test Application Time Through Test Data Mutation Encoding PowerPoint Presentation
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Reducing Test Application Time Through Test Data Mutation Encoding

Reducing Test Application Time Through Test Data Mutation Encoding

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Reducing Test Application Time Through Test Data Mutation Encoding

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  1. Reducing Test Application Time Through Test Data Mutation Encoding Sherief Reda and Alex Orailoglu Computer Science Engineering Dept. University of California, San Diego

  2. Outline Introduction Motivation Test Data Mutation Encoding Scheme overview Overlap exploration Computational aspects Don’t care handling Hardware challenges Time Reduction Analysis Experimental Results Conclusions

  3. Increased test application time hinders volume manufacturing in today’s demanding market. Introduction Advancements in VLSI device fabrication  Unprecedented integration levels High integration manufacturing  Increased test application time Testing multiple cores on System-on-a-Chip (SoC)  Increased test application time

  4. Scan chain length Mutate 0 X Test time increase X X X X 1 1 Flip 0 1 X X 1 X Mutation reduces test time by specifying only the bits to be flipped X 1 X 1 1 X Problem: Test responses destroy the scan cells’ content! X 1 X 0 Flip 0 1 X 0 X X X 0 Motivation TDI TDO Test Vector I Test Vector II LFSR

  5. 0 Decompose scan chain X X 1 1 1 X 0 X 1 X 1 1 1 X X X X X 1 0 X 1 1 0 1 1 1 1 X X X 0 X X 1 X X X 1 1 X X X 1 0 X Bits to specify inversion Large test vectors are transformed into small horizontal test slices Scan chain length X Small number of bits to specify an inversion Small test slice Motivation TDI TDO LFSR

  6. 0 Decompose scan chain X X 1 1 X 1 1 1 X X X 1 0 X Bits to specify inversion Large test vectors are transformed into small horizontal test slices Scan chain length X Small number of bits to specify an inversion Small test slice Motivation TDI 0 1 1 1 0 1 1 0 0 1 1 0 1 1 1 0 TDO LFSR

  7. DSR TDI: Test Data Input 0 TDI 0 0 DSR: Decoder Shift Register 0 DOR: Decoder Output Register 1 TDO: Test Data Output 2x4 Decoder 1 1 Flip 1 ENABLE Mutated Test Slice 1 1 1 0 0 0 0 0 DOR 0 1 CLK 1 1 1 0 1 0 0 MISR 0 Test Data Mutation Encoding 0011011 3(11) 2(10) 1(01) 0(00) Bits 2 & 3 need to be flipped 10, 11 to be injected = 4 bits Overlap can reduce this to just 11 = 2 bits TDO

  8. TDI: Test Data Input 0 DSR: Decoder Shift Register 0 DOR: Decoder Output Register 1 TDO: Test Data Output 1 1 1 Mutated Test Slice 1 1 1 0 0 1 1 1 1 0 1 0 0 0 Test Data Mutation Encoding DSR TDI 001101 0 1 2x4 Decoder 3(11) 2(10) 1(01) 0(00) Flip ENABLE 0 1 0 DOR 0 CLK Bits 2 & 3 need to be flipped 10, 11 to be injected = 4 bits Overlap can reduce this to just 11 = 2 bits MISR TDO

  9. TDI: Test Data Input 0 DSR: Decoder Shift Register 0 DOR: Decoder Output Register 1 TDO: Test Data Output 1 1 1 Mutated Test Slice 1 1 1 0 0 1 1 1 1 0 1 0 0 0 Test Data Mutation Encoding DSR TDI 00110 1 1 2x4 Decoder 3(11) 2(10) 1(01) 0(00) Flip ENABLE 1 1 0 0 DOR CLK Bits 2 & 3 need to be flipped 1 0 1 0 10, 11 to be injected = 4 bits Overlap can reduce this to just 11 = 2 bits MISR TDO

  10. TDI: Test Data Input 0 DSR: Decoder Shift Register 0 DOR: Decoder Output Register 1 TDO: Test Data Output 1 1 1 Mutated Test Slice 1 1 1 1 0 1 1 1 1 0 1 0 0 0 Test Data Mutation Encoding DSR TDI 0011 1 0 2x4 Decoder 3(11) 2(10) 1(01) 0(00) Flip ENABLE 1 1 1 0 DOR CLK 1 1 1 0 1 0 0 1 MISR TDO

  11. TDI: Test Data Input 0 DSR: Decoder Shift Register 0 DOR: Decoder Output Register 1 TDO: Test Data Output 1 1 1 Mutated Test Slice 1 0 1 1 0 1 1 1 1 0 1 0 0 0 Test Data Mutation Encoding DSR TDI 001 0 1 2x4 Decoder 3(11) 2(10) 1(01) 0(00) Flip ENABLE 1 1 1 0 DOR CLK 1 1 1 0 1 0 0 1 MISR TDO

  12. TDI: Test Data Input 0 DSR: Decoder Shift Register 0 DOR: Decoder Output Register 1 TDO: Test Data Output 1 1 1 Mutated Test Slice 1 0 1 1 0 1 1 1 1 0 1 0 0 0 Test Data Mutation Encoding DSR TDI 00 1 1 2x4 Decoder 3(11) 2(10) 1(01) 0(00) Flip ENABLE 0 1 1 0 DOR CLK 1 1 0 0 1 0 1 1 1 0 1 0 MISR TDO

  13. TDI: Test Data Input 0 DSR: Decoder Shift Register 0 DOR: Decoder Output Register 1 TDO: Test Data Output 1 1 1 Mutated Test Slice 1 0 1 1 1 1 1 1 1 0 1 0 0 0 Test Data Mutation Encoding DSR TDI 0 1 0 2x4 Decoder 3(11) 2(10) 1(01) 0(00) Flip ENABLE 0 1 1 0 DOR CLK 1 1 0 0 1 0 1 1 1 0 0 1 MISR TDO

  14. TDI: Test Data Input 0 DSR: Decoder Shift Register 0 DOR: Decoder Output Register 1 TDO: Test Data Output 1 1 1 Mutated Test Slice 1 0 1 1 1 1 1 1 1 0 1 0 0 0 Test Data Mutation Encoding DSR TDI 0 0 2x4 Decoder 3(11) 2(10) 1(01) 0(00) Flip ENABLE 0 1 1 1 DOR CLK 7 clock cycles are needed to inject 21 bits through 3 parallel streams to mutate the test vector. 1 1 0 1 1 1 0 0 1 1 1 0 1 0 1 0 57% reduction in test application time MISR TDO

  15. Fundamental Challenges Input test data indicates flips needed to mutate test slices. Input test data encodes the indices of flip locations. Optimal ordering of the indices  maximal overlap  minimal test application time. Problem: What is the flipping order that attains the minimal number of clock cycles?

  16. 0 1 Overlap Exploration TDI 0 0 0 000 100 3x8 Decoder MISR TDO

  17. 0 1 0 1 Overlap Exploration TDI 1 0 0 000 100 3x8 Decoder 010 110 MISR TDO

  18. 0 TDI 0 1 1 0 1 1 3x8 Decoder 0 0 1 0 0 1 1 1 0 0 1 MISR TDO 1 Overlap Exploration 0 000 4 1 100 001 2 010 5 101 3 6 110 011 7 111 State Transition Diagram of DSR (DeBruijn Diagram)

  19. 0 1 2 3 6 5 7 4 0 3 2 3 1 3 2 3 0 1 0 2 3 1 3 2 3 1 2 2 1 0 3 2 1 2 3 3 2 1 2 0 2 1 2 3 4 3 2 1 2 0 2 1 2 5 3 2 3 2 3 0 1 2 6 3 2 3 1 3 2 0 1 7 3 2 3 1 3 2 3 0 Distance Matrix Objective: Mutating an 8 bit test slice through flipping bits 2 & 6 Overlap Exploration 0 0 0 000 1 4 1 1 100 001 2 010 0 0 1 5 0 0 1 101 1 1 3 6 0 110 011 7 0 1 111 1 State Transition Diagram of DSR (DeBruijn Diagram)

  20. 0 1 2 3 6 5 7 4 0 3 2 3 1 3 2 3 0 1 0 2 3 1 3 2 3 1 2 2 1 0 3 2 1 2 3 3 2 1 2 0 2 1 2 3 4 3 2 1 2 0 2 1 2 5 3 2 3 2 3 0 1 2 6 3 2 3 1 3 2 0 1 7 3 2 3 1 3 2 3 0 Distance Matrix First option: 4-2-6 yields 3 clock cycles Objective: Mutating an 8 bit test slice through flipping bits 2 & 6 Overlap Exploration 0 0 0 000 1 4 1 1 100 001 2 010 0 0 1 5 0 0 1 101 1 1 3 6 0 110 011 7 0 1 111 1 State Transition Diagram of DSR (DeBruijn Diagram)

  21. 0 1 2 3 6 5 7 4 0 3 2 3 1 3 2 3 0 1 0 2 3 1 3 2 3 1 2 2 1 0 3 2 1 2 3 3 2 1 2 0 2 1 2 3 4 3 2 1 2 0 2 1 2 5 3 2 3 2 3 0 1 2 6 3 2 3 1 3 2 0 1 7 3 2 3 1 3 2 3 0 Distance Matrix Second option: 4-6-2 yields 4 clock cycles Objective: Mutating an 8 bit test slice through flipping bits 2 & 6 Overlap Exploration 0 0 0 000 1 4 1 1 100 001 2 010 0 0 1 5 0 0 1 101 1 1 3 6 0 110 011 7 0 1 111 1 State Transition Diagram of DSR (DeBruijn Diagram)

  22. Computational Aspects Optimal number of test bits  Enumerating all the possible trips to pick the one that achieves the minimal total distance If there are n bits to flip, then there are n! trips to consider in order to calculate the optimal trip Large number of flips  Enumeration of all trips is computationally infeasible  A greedy strategy is utilized

  23. Greedy strategy - Move from the initial state to the closest state. - Repeat until the test slice is mutated: Move from the current state to the closest next state corresponding to the bit index to be flipped Objective: Mutating an 8 bit test slice through flipping bits 5, 6 & 7 Computational Aspects 0 0 0 000 1 4 1 1 100 001 2 010 0 0 1 0 5 0 1 101 1 1 3 6 0 110 011 7 0 1 111 1 Greedy strategy is applied to visit the three states

  24. Greedy strategy - Move from the initial state to the closest state. - Repeat until the test slice is mutated: Move from the current state to the closest next state corresponding to the bit index to be flipped Objective: Mutating an 8 bit test slice through flipping bits 5, 6 & 7 Computational Aspects 0 0 0 000 1 4 1 1 100 001 2 010 0 0 1 0 5 0 1 101 1 1 3 6 0 110 011 7 0 1 111 1 Greedy strategy is applied to visit the three states

  25. Greedy strategy - Move from the initial state to the closest state. - Repeat until the test slice is mutated: Move from the current state to the closest next state corresponding to the bit index to be flipped Objective: Mutating an 8 bit test slice through flipping bits 5, 6 & 7 Computational Aspects 0 0 0 000 1 4 1 1 100 001 2 010 0 0 1 0 5 0 1 101 1 1 3 6 0 110 011 7 0 1 111 1 Greedy strategy is applied to visit the three states

  26. Greedy strategy - Move from the initial state to the closest state. - Repeat until the test slice is mutated: Move from the current state to the closest next state corresponding to the bit index to be flipped Objective: Mutating an 8 bit test slice through flipping bits 5, 6 & 7 Computational Aspects 0 0 0 000 1 4 1 1 100 001 2 010 0 0 1 0 5 0 1 101 1 1 3 6 0 110 011 7 0 1 111 1 Greedy strategy is applied to visit the three states

  27. 76543210 11100110 x0xxx0xx xxxxxxxx xxxxxxxx 1x0xx0xx Don’t Care Handling Test Slice A Test Slice B Test Slice C Test Slice D Test Slice E

  28. 76543210 11100110 x0xxx0xx xxxxxxxx xxxxxxxx 1x0xx0xx Don’t Care Handling Test Slice A Test Slice B Test Slice C Test Slice D Test Slice E There are 2 cases: A run of don’t cares in between two identical specified bits A run of don’t cares in between two distinctly specified bits

  29. 76543210 11100110 10xxx0xx 1xxxxxxx 1xxxxxxx 1x0xx0xx Don’t Care Handling Test Slice A Test Slice B Test Slice C Test Slice D Test Slice E There are 2 cases: A run of don’t cares in between two identical specified bits A run of don’t cares in between two distinctly specified bits

  30. x0xxx0xx 10100010 0x0xxxxx 00000010 6 clock cycle Don’t Care Handling 0 0 Assume we have the 3 test slices. 0 000 1 4 1 1 100 001 76543210 76543210 2 11100110 11100110 010 Test Slice A 0 0 x0xxx0xx Test Slice B 5 1 0 0 1 0x0xxxxx Test Slice C 101 1 1 3 6 0 110 011 7 0 1 111 A B 3 Clock Cycles

  31. 10100010 00000010 6 clock cycle Don’t Care Handling 0 0 Assume we have the 3 test slices. 0 000 1 4 1 1 100 001 76543210 76543210 2 11100110 11100110 010 Test Slice A 0 0 x0xxx0xx Test Slice B 5 1 0 0 1 0x0xxxxx Test Slice C 101 1 1 3 6 0 110 011 7 0 1 111 B C 3 Clock Cycles

  32. Don’t Care Handling 0 0 Assume we have the 3 test slices. 0 000 1 4 1 1 100 001 76543210 76543210 2 11100110 11100110 010 Test Slice A 0 0 10000010 x0xxx0xx Test Slice B 5 1 0 0 1 00000010 0x0xxxxx Test Slice C 101 1 1 3 4 clock cycles 6 0 110 011 A B 7 0 1 111 3 Clock Cycles 1 While mutating test slice A to test slice B we can flip bit 5 in anticipation for test slice C. This saves 2 bits in mutating test slice B to C.

  33. Don’t Care Handling 0 0 Assume we have the 3 test slices. 0 000 1 4 1 1 100 001 76543210 76543210 2 11100110 11100110 010 Test Slice A 0 0 10000010 x0xxx0xx Test Slice B 5 1 0 0 1 00000010 0x0xxxxx Test Slice C 101 1 1 3 4 clock cycles 6 0 110 011 B C 7 0 1 111 1 Clock Cycle 1 While mutating test slice A to test slice B we can flip bit 5 in anticipation for test slice C. This saves 2 bits in mutating test slice B to C.

  34. Reducing I/O Pin Requirements TDI TDO/Enable Enable 2x4 decoder v CLK Control v TDO MISR To alleviate the requirement of adding an extra ENABLE pin, one of the I/O pins can be multiplexed or the TDO can be multiplexed.

  35. Fundamental Issues How many scan chains should the original scan chain be decomposed into? What is the decoder size to be used? What is the attainable time reduction for various scan chain configurations? What is the relation between the number of flips to be performed in mutating test slices and the achievable time reduction?

  36. Outline Introduction Motivation Test Data Mutation Encoding Scheme overview Overlap exploration Computational aspects Don’t care handling Hardware requirements Time Reduction Analysis Experimental Results Conclusions

  37. 0 1 0 0 0 1 X 0 0 1 2 2 X X 0 0 0 1 4 3 X X X 0 1 0 0 1 2 1 X 0 0 2 X X 0 2 Weighted average shifts for state 000: 2.125 cycles 3 X X X 3 Weighted average shifts for state 001: 1.875 cycles Time Reduction Analysis If we only need to flip one bit to mutate the current test slice to the next test slice, how many shift clock cycles are needed? 0 New Reachable States Next State Initial State Shifts 000 0 1 TDI 0 0 0 0 0 0 1 100 001 3x8 Decoder 010 0 0 1 0 1 0 1 1 101 0 110 011 MISR TDO 1 0 111 1 State transition diagram of the decoder shift register Hardware Organization

  38. Time Reduction Analysis Given an initial state, what is the average number of clock cycles needed to reach a different state? 1.84 clock cycles. The average number of clock cycles needed to reach a combination of states is not only function of the initial state but also of the particular combination of states to be visited.

  39. Time Reduction Analysis Test Slice Size In general, what is the average number of clock cycles needed to mutate the test slices of various sizes?

  40. Time Reduction Analysis Test Slice Size Test Slice Size Test Slice Size Time Reduction Ratio = Average number of shift clock cycles

  41. Time Reduction Analysis Test Slice Size Bits to Flip x Test slice size/4 In this experiment, we assume that the number of bits to be flipped to mutate a 32 bit test slice is 8 times the number of bits to be flipped to mutate a 4 bit slice.

  42. Experimental Results MinTest fully specified vectors are compressed using test data mutation Compressing MinTest vectors results in an average time reduction ratio of 2.4 for the 5 benchmark circuits MinTest: Hamzaoglu & Patel, ITC, 1998 Virtual Scan Chains: Jas & Touba, VTS, 2000 Golomb Coding: Chandra & Chakrabarty, VTS, 2000 Test Data Mutation using MinTest fully specified vectors

  43. Experimental Results Test Data Mutation is applied to incompletely specified test vectors obtained from Atalanta Compressing the incompletely specified test vectors, using last flip heuristic, results in an average time reduction ratio of 6.7 in comparison with MinTest for the 5 benchmark circuits MinTest: Hamzaoglu & Patel, ITC, 1998 MinTest: Hamzaoglu & Patel, ITC, 1998 Test Data Mutation using MinTest fully specified vectors Test Data Mutation using incompletely specified vectors

  44. Experimental Results Augmenting Scan Chain Concealment results in an increased test time reduction by a factor of 1.8 Scan Chain Concealment: Bayraktaroglu, Orailoglu, DAC, 2001 Test Data Mutation using scan chain concealment fully specified vectors

  45. Conclusions A new methodology to reduce test application time through test data mutation is presented Effective overlapping of test data yields huge reductions in test application time Reduced hardware overhead Thorough analysis of the proposed method identifies configurations and conditions for optimal test time reduction Experimental results on ISCAS’89 benchmarks confirm drastic test time application reductions