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AHPL&VHDL. Hardware Description Languages: a Comparison of AHPL and VHDL. By Tamas Kasza. A presentation for. Digital System Design 1 (ECE 5571) Spring 2003. AHPL&VHDL. Content. Introduction Brief History of Hardware Description Languages (HDLs) The Roles and Relationship of AHPL and VHDL

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Hardware Description Languages: a Comparison of AHPL and VHDL


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    1. AHPL&VHDL Hardware Description Languages: a Comparison of AHPL and VHDL By Tamas Kasza A presentation for Digital System Design 1 (ECE 5571) Spring 2003

    2. AHPL&VHDL Content Introduction • Brief History of Hardware Description Languages (HDLs) • The Roles and Relationship of AHPL and VHDL Main Similarities and Differences between AHPL and VHDL – a small case study Challenges and Future of HDLs – Summary and Discussion

    3. AHPL&VHDL Introduction HDLs – Hardware Description Languages Why are they useful? • Maximum reliability with low-cost and time-effective development • Design&Documentation at the same time • Testing&Simulation is easy • Maintenance is easy • FPGAs and ASICs have become widely used • Powerful design tools

    4. AHPL&VHDL HDLs HDLs – Hardware Description Languages Examples: • ABEL: • Simplified HDL • Dataflow primitives, e.g., registers • Can use to Program XILINX FPGA • ALTERA • Created by Altera Corporation • Simplified dialect of HDL • AHDL: Altera Hardware Description Language

    5. AHPL&VHDL HDLs - Examples • CDL: Computer Design Language • Academic language for teaching digital systems • Dataflow language • Non-hierarchical • Contains conditional statements • CONLAN: CONsensus LANguage • Family of languages for describing various levels of abstraction • Concurrent • Hierarchical

    6. AHPL&VHDL HDLs - Examples • IDL: Interactive Design Language • Internal IBM language • Originally for automatic generation of PLA structures • Generalized to cover other circuits • Concurrent • Hierarchical • CDL: Computer Design Language • ISPS: Instruction Set Processor Specification • Behavioral language • Used to design software based on specific hardware • Statement level timing control, but no gate level control

    7. AHPL&VHDL HDLs - Examples • TEGAS: TEst Generation And Simulation • Structural with behavioral extensions • Hierarchical • Allows detailed timing specifications IDL: Interactive Design Language • TI-HDL: Texas Instruments Hardware Description Language • Created at Texas Instruments • Hierarchical • Models synchronous and asynchronous circuits • Non-extendable fixed data types

    8. AHPL&VHDL • Verilog • Essentially identical in function to VHDL • No generate statement • Simpler and syntactically different • C-like • Gateway Design Automation Co., 1983 • Early de facto standard for ASIC programming • ZEUS • Created at General Electric • Hierarchical • Functional Descriptions • Structural Descriptions • Clock timing, but no gate delays • No asynchronous circuits HDLs - Examples

    9. AHPL&VHDL Introduction - HDLs AHPL – A Hardware Programming Language • First published in 1973 • Widely used in the 70s and 80s • It has been successfully tested on a broad spectrum of design problems • Characteristics: • Dataflow language • Implicit clock • Does not support asynchronous circuits • Fixed data types • Non-hierarchical

    10. AHPL&VHDL Introduction - HDLs VHDL – VHSIC (Very High Speed Integrated Circuit) Hardware Description Language • Introduced in 1980: • Object was to achieve significant gains in VLSI technology by shortening the time from concept to implementation (18 months to 6 months) • Need for a common descriptive and simulation language • August 1985: VHDL Version 7.2 released • December 1987: VHDL became IEEE Standard and in 1988 an ANSI standard • September 1993: restandardization of VHDL in order to clarify and enhance the language • 2001: Revised IEEE VHDL Standard

    11. AHPL&VHDL x carry y Half Adder result enable Case Study • Problem: Develop a combinational logic unit description of a half adder. • Specification: • Input and output are both one bit • When enable is 1(high), result gets x plus y • When enable is 1(high), carry gets any carry of x plus y • Outputs are zero when enable input is low

    12. AHPL&VHDL Case Study – AHPL • CLUNIT: HALFADD (x; y; enable) • INPUTS: x; y; enable. • OUTPUTS: HALFADD[2]. • CTERMS: a; carry; result. • BODY • a = xy; • result = a enable; • carry = x y enable; • HALFADD[0] = carry; • HALFADD[1] = result; • END

    13. AHPL&VHDL x carry y Half Adder result enable Case Study – VHDL First step: entity declaration describes the (input and output) interfaces of the component ENTITY half_adder IS PORT( x, y, enable: IN BIT; carry, result: OUT BIT); END half_adder;

    14. AHPL&VHDL Case Study – VHDL ARCHITECTURE half_adder_a OF half_adder IS BEGIN PROCESS (x, y, enable) BEGIN IF enable = ‘1’ THEN result <= x XOR y; carry <= x AND y; ELSE carry <= ‘0’; result <= ‘0’; END IF; END PROCESS; END half_adder_a;

    15. AHPL&VHDL VHDL – Timing Behavior ARCHITECTURE half_adder_b OF half_adder IS BEGIN PROCESS (x, y, enable) BEGIN IF enable = ‘1’ THEN result <= x XOR y after 10ns; carry <= x AND y after 12 ns; ELSE carry <= ‘0’ after 10ns; result <= ‘0’ after 12ns; END IF; END PROCESS; END half_adder_b;

    16. AHPL&VHDL VHDL – Pure Logical ARCHITECTURE half_adder_c OF half_adder IS BEGIN carry <= enable AND (x AND y); result <= enable AND (x XOR y); END half_adder_c;

    17. AHPL&VHDL VHDL – Component Based ARCHITECTURE half_adder_d OF half_adder IS COMPONENT and2 PORT (in0, in1 : IN BIT; out0 : OUT BIT); END COMPONENT; COMPONENT and3 PORT (in0, in1, in2 : IN BIT; out0 : OUT BIT); END COMPONENT; COMPONENT xor2 PORT (in0, in1 : IN BIT; out0 : OUT BIT); END COMPONENT; FOR ALL : and2 USE ENTITY gate_lib.and2_Nty(and2_a); FOR ALL : and3 USE ENTITY gate_lib.and3_Nty(and3_a); FOR ALL : xor2 USE ENTITY gate_lib.xor2_Nty(xor2_a); SIGNAL xor_res : BIT; -- internal signal BEGIN A0 : and2 PORT MAP (enable, xor_res, result); A1 : and3 PORT MAP (x, y, enable, carry); X0 : xor2 PORT MAP (x, y, xor_res); END half_adder_d;

    18. AHPL&VHDL AHPL – VHDL Comparison

    19. AHPL&VHDL The Most Important Features An effective HDL in the 21st century should • Be hierarchical, modularized  Complexity has been growing • Contain application specific features • Be conform to other widely used HDLs (mapping, remapping, etc.) • Be easy to understand and maintain by engineers • Contain graphical, as well as textual notation parts … What else?

    20. Thank You for Your Attention!