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Understanding ISAs: Instruction and Data Types Analysis with Addressing Modes

Explore the world of Instruction Set Architectures (ISAs) in this lecture series, diving into instruction types, data formats, and various addressing modes. Topics include ISA principles like good design and simplicity, instruction formats, DLX and x86 ISA comparison, RISC vs. CISC architectures, and compiler optimizations.

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Understanding ISAs: Instruction and Data Types Analysis with Addressing Modes

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  1. Lecture 6: ISAs Continued Last Time: Instruction types Data types Addressing modes Today Quantitative Analysis (by example) Instruction Formats DLX review x86 ISA (brief) RISC vs. CISC Compiler optimizations

  2. Review of ISA Principles • Good ISA design • KISS! - only implement necessities (encodings, address modes, etc.) • FOG: Frequency, Orthogonality, Generality • Instruction Types • ALU ops, Data movement, Control • Addressing modes • Matched to program usage (local vars, globals, arrays) • Program Control • Conditional/unconditional branches and jumps • Where to store conditions • PC relative and absolute

  3. 6 5 5 5 11 Op RS1 RS2 RD func 6 5 5 16 Op RS1 RD Const 6 26 Op Const Instruction Formats • Different instructions need to specify different information • return • increment R1 • R3  R1 + R2 • jump to 64-bit address • Frequency varies • instructions • constants • registers • Can encode • fixed format • small number of formats • byte/bit variable R: rd  rs1 op rs2 I: ld/st, rd  rs1 op imm, branch J: j, jal Fixed-Format (DLX)

  4. 8 Op 4 4 4 4 4 4 4 4 4 4 R R R R R M M M M M Variable-Length Instructions • Variable-length instructions give more efficient encodings • no bits to represent unused fields/operands • can frequency code operations, operands, and addressing modes • Examples • VAX-11, Intel x86 (byte variable) • Intel 432 (bit variable) • But - can make fast implementation difficult • sequential determination of location of each operand 8 Op 8 Op 8 32 Op Disp VAX instrs: 1-53 bytes!

  5. Compromise: A Few Good Formats • Gives much better code density than fixed-format • important for embedded processors • Simple to decode 6 5 5 5 1 10 Op R1 R2 R3 Const 6 5 5 Op R1 R2 4 4 4 4 Op R1 R2 R3

  6. Integer constants mostly small positive or negative Bit fields contiguous field of 1s within 32bits (64 bits) Other addresses, characters, symbols A good architecture uses a few bits to encode the most common. allows any constant to be generated (table reference) Constant Encoding VAX short literal -32 to 31 6 Op 5 5 E S Symbolics 3600 Bit Fields 00000001111111111000000000000000

  7. DLX ISA • 32 GP Integer registers, 32 FP registers (16 DP) • R0 = 0 • 8, 16, and 32 bit data types • Load/Store architecture (no memory operations in ALU ops) • Simple addressing modes • Immediate R1  0x23 • Displacement R2  d(Rx) ….. 0(R3), 0x1000(R0) • Simple fixed instruction format (3 types), 90 instructions • Similar to MIPS instruction set • Designed for fast hardware (pipelining) + optimizing compilers

  8. 6 5 5 5 11 Op RS1 RS2 RD func 6 5 5 16 F30 F2 F3 F31 Op RS1 RD Const F0 F1 6 26 Op Const DLX ISA (a visual) IP R: rd  rs1 op rs2 R31 I: ld/st, rd  rs1 op imm, branch R1 R0 J: j, jal Fixed-Format

  9. What is a RISC? (Reduced Instruction Set Computer) no firm definition generally includes general registers fixed 3-address instruction format strict load-store architecture simple addressing modes simple instructions Examples DEC Alpha MIPS Advantages good compiler target easy to implement/pipeline CISC (Complex Instruction-Set Computer) CISC  RISC may include variable length instructions memory-register instructions complex addressing modes complex instructions CALLP, EDIT, … Examples DEC VAX, IBM 370, x86 Advantages better code density legacy software CISC vs RISC

  10. Role of the Optimizing Compiler C source code Front End (Language Specific) IR Procedure InliningLoop Transformations HW/SW complexity tradeoffs High-Level Optimizations IR Common SubExp Elim. Code Motion Global Optimizations Machine-IR Instruction Scheduling Register Allocation Machine Dependent Code Generator Machine binary code

  11. Example: Loop Optimization sum=0; for(i=0;i<max;i++) sum+=x[i]; LW R1, X ADD R2,R0,#MAX SLLI R2,R2,#2 ADD R2,R1,R2 ADD R3,R0,R0 LOOP: LW R4,R1 ADD R3,R3,R4 ADD R1,R1,#4 SLT R5,R1,R2 BNEZ R5,LOOP CONT: LW R1, X ADD R2,R0,R0 ADD R3,R0,R0 LOOP: SLT R5,R2,#MAX BEQZ R5,CONT LW R4,R1 ADD R3,R3,R4 ADD R1,R1,#4 ADD R2,R2,#1 J LOOP CONT: 5 7 LW R1, X ADD R2,R0,R0 ADD R3,R0,R0 LOOP: LW R4,R1 ADD R3,R3,R4 ADD R1,R1,#4 ADD R2,R2,#1 SLT R5,R2,#MAX BNEZ R5,LOOP CONT: 6 Loop Reordering Induction Variable Analysis

  12. Architect  Compiler Writer • Simplify, Simplify, Simplify • Feature difficult to use, it won’t be used….Less is More! • Regularity • Common set of formats, few special cases • Primitive, not solutions • CALLS vs. Fast register moves • Make performance tradeoffs simple • Ultimately, the ISA will *not* be perfect

  13. Compiler  Microarchitecture • Instruction Scheduling • Instruction Level Parallelism • Resource Allocation • Registers (minimize spills/restores to and from memory) • Memory optimizations • Cache conscious data organization • Code layout • Etc…...

  14. Next Time • MICROARCHITECTURE!!!!! • Enough with the paint job - what’s under the hood! • Logic Design Review • Registers • Multiplexors • Arithmetic units • Simple DLX processor

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