Leveraging Heterogeneity in DRAM Main Memories for Accelerating Critical Word Access

1. Leveraging Heterogeneity in DRAM Main Memories to Accelerate Critical Word Access N. Chatterjee, M. Shevgoor, R. Balasubramonian, A. Davis, Z. Fang*‡, R. Illikkal†, and R. Iyer† University of Utah, Intel Labs† and Nvidia*(work done while at Intel) ‡ DRAM Variants RLDRAM/LPDDR Heterogeneous Memory RLDRAM DDR DDR4 DDR2 DDR3 4 Sub-Ranked Channels of RLDRAM, each 0.25GB Data RLDRAM 0.25GB Data 4 such Data and Add/Cmd Channels 4 such LPDRAM channels LPDDR Ch0 Ch2 Ch1 Ch3 Heterogeneous Memory Processor 8-bit Data + 1-bit Parity 26-bit Addr/Cmd (b) Heterogeneous System with CWA (c) Proposed System (a) Baseline DDR3 System MC0 RLMC MRC0 38-bit Addr/Cmd 72-bit Data +ECC 8-bit Data + 1-bit parity RLDRAM Channel 23-bit Addr/Cmd Processor Processor MC0 MC0 4 such DDR3 channels Critical Word Regularity 64-bit Data + ECC 23-bit Addr/Cmd 2GB DDR3 DRAM DIMM 23-bit Addr/Cmd 64-bit Data +ECC 4 such LPDDR channels • Word-0 is the critical word 67% of the time • Fetch Critical-Word from RLDRAM • Fetch Non-Critical words LPDDR • Average gap between first and second access > LPDDR latency 82% of the time LPDRAM DIMM 1.75GB Data+ ECC (4 such channels) LPDRAM DIMM 1.75GB Data+ ECC • Heterogeneous memory system includes low-latency RLDRAM and low-energy LPDRAM • Average main memory access time of RLDRAM3 is 43% lower than that of DDR3 Results • Average Performance improvement of 12.9% • 22% reduction in average Latency • Memory Energy reduction of 15% • System Energy reduction of 6%

2. Leveraging Heterogeneity in DRAM Main Memories to Accelerate Critical Word Access Heterogeneous Memory LPDDR DDR3 CPU CPU RLDRAM RLDRAM DDR3 DDR3 DDR3 LPDDR