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EET 423 POWER ELECTRONICS -2

EET 423 POWER ELECTRONICS -2. PWM CONTROL. CLOSED LOOP REGULATION. FEEDBACK CONTROL LOOP. MOSFET. SMPS. L O A D. V out sense. V out. E in. CURRENT sense. PWM ic. MEASUREMENT (SENSING). POTENTIAL DIVIDER. R H R L temperature stability. important. R H. L O A D. V out.

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EET 423 POWER ELECTRONICS -2

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  1. EET 423 POWER ELECTRONICS -2 PWM CONTROL CLOSED LOOP REGULATION

  2. FEEDBACK CONTROL LOOP MOSFET SMPS L O A D Vout sense Vout Ein CURRENT sense PWM ic

  3. MEASUREMENT (SENSING) POTENTIAL DIVIDER RH RLtemperature stability important RH L O A D Vout RH RL 1% TOLERANCE RL

  4. PWM ic : UC3823 A /B series BASICALLY a BUILDING BLOCK: like OP- AMPS NEED to DESIGN AROUND

  5. PWM ic : FREQUENCY RT CT GND internal oscillator frequency determined by external timing resistor RT and timing capacitor CT

  6. i.c. DATA SHEET RT determines maximum duty cycle limited by the time needed to reset the ramp to zero each cycle

  7. PWM ic: CURRENT LIMIT-SHUTDOWN VIsense RI1 VI limit RI2 1.0V <VI limit < 1.2 V CURRENT LIMIT MODE GND followed by return to operating Dsw when VI limit GOES <1.0 V

  8. PWM ic: CURRENT LIMIT-SHUTDOWN VIsense RI1 VI limit RI2 VI limit > 1.2 V CURRENT SHUT DOWN MODE GND followed by return to soft-start up when VI limit GOES < 1.2 V

  9. PWM ic: SOFT START CSS GND

  10. PWM ic: LEADING EDGE BLANKING CLEB GND

  11. INTERNAL 5.1 V DC SUPPLY INTERNALLY GENERATED HIGHLY REGULATED 5.1 V DC POWERS INTERNAL CIRCUITRY

  12. INTERNAL 5.1 V DC SUPPLY RR1 VREF, new RR2 CREATE EXTERNAL REFERENCE VOLTAGE GND

  13. PWM PULSE GENERATION Ein Dsw Vdc COMPARATOR - + Vramp Vdc Vramp o HIGH: Vdc >Vramp o Dsw Tsw Tsw

  14. WHERE DO THERAMP&DC VOLTAGESCOME FROM ????? RAMP from CT CT GND DC from EAout

  15. PWM PULSE GENERATION Ein INTERNAL ic COMPARATOR Dsw Vdc - + Vramp CT RAMP NOT COMPARATOR INPUT internal 1.25 Vshift to avoid possible comparator jitter due to zero reference noise.

  16. PWM PULSE GENERATION DVramp Vramp peak 2.8 V Vramp.CT Vramp valley 1V 0 4.05 V Vcomp- 2.25 V Vcomp+ 1.25 Vshift 0 PWM output 0 Tsw Dsw Tsw

  17. ERROR AMPLIFIER INTERNAL ERROR AMPLIFIER Ein RF Vdc Dsw RS Vsense - - + + VEA,refdc Vramp

  18. ERROR AMPLIFIER Ein Vdc RF Dsw RS - - + + VEA,out Vsense Vdiff Vramp VEA,ref Op-amp theory V(-) → V(+)

  19. COMPARATOR: DUTY CYCLE similar triangles

  20. VARIABLE DUTY CYCLE

  21. 2.8 V Vramp 1V error amp output 3 0 4.05 V error amp output 2 error amp output 1 2.25 V pwm comp 0 PWM output D1swT T D2swT T D3swT T T VARIABLE DUTY CYCLE

  22. PWM CLOSED LOOP REGULATION Vout(nom) Vout< Vout(nom) Vout> Vout(nom) VEA,ref VEA,ref VEA,ref Vdiff Vdiff Vdiff Vsense Vsense Vsense NORMAL Dsw Vout Vdiff VEAout Vsense Vout Vout Vsense Vdiff Vout VEAout Dsw Vsense >VEAref J  Vsense <VEAref @ Vout,max X L

  23. REGULATION REQUIREMENTS • Vsense,out < VEA,ref at Vout,max and Iout,min • VEA,out in DVramp range ; 2.25 < VEA,out < 4.05 • Dsw if Ein  or Vout  or Iout  • Dsw if Ein  or Vout  or Iout 

  24. SMPS CLOSED LOOP REGULATION NR : NP : NS D1 rind Iout L C Vout R D2 Ein f SW DSW RSENSE Vout + RH VS,out RT CT RL gnd gnd 5.1 V gnd REA1 RF r Vout - Vr VS,out VI,sense REA2 RS CSS gnd RS1 gnd VI,limit RS2 gnd

  25. SMPS CLOSED LOOP DESIGN PROCEDURE: Vout, lower  Vsense,lower  requires Dsw,higher  requires VEAout,higher when Ein, lower or Iout,higher

  26. SMPS CLOSED LOOP DESIGN PROCEDURE: Vout,higher  Vsense,higher  requires Dsw,lower  requires VEAout,lower when Ein, higher or Iout,lower

  27. SMPS CLOSED LOOP DESIGN

  28. SMPS CLOSED LOOP DESIGN

  29. SMPS CLOSED LOOP DESIGN

  30. OUTPUT VOLTAGE SENSING: GAIN FACTOR Feedback Theory Vsense → VEA,ref

  31. GAIN FACTOR: TOLERANCE VEAref CONSTANT Vout TOLERANCE = GAIN FACTOR TOLERANCE  Vout TOLERANCE = fn RLS & RHS TOLERANCE

  32. USE LOW TOLERANCE SENSING RESISTORS

  33. TEMPERATURE COEFFICIENT of RESISTANCE USE LOWER ppm / oC SENSING RESISTORS

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