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A Signature Match Processor Architecture for Network Intrusion Detection

A Signature Match Processor Architecture for Network Intrusion Detection. Authors : Janardhan Singaraju,Long Bu and John A. Chandy, Publisher : IEEE Symposium on Field-Programmable Custom Computing Machines Present: Kia-Tso Chang Date: December 13 2007. 1. outline.

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A Signature Match Processor Architecture for Network Intrusion Detection

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  1. A Signature Match Processor Architecture for Network Intrusion Detection Authors: Janardhan Singaraju,Long Bu and John A. Chandy, Publisher: IEEE Symposium on Field-Programmable Custom Computing Machines Present: Kia-Tso Chang Date: December 13 2007 1

  2. outline • Signature Match Processor • Character Match Array • Signature Match Array • Address Output Logic • Performance Analysis • FPGA implementation

  3. Signature Match Processor Architecture

  4. Character Match Array

  5. Signature Match Array 5

  6. pseudo-VHDL (p = 4)

  7. SMP Example

  8. Addition of a Cache

  9. match address outputlogic ( MAO logic)

  10. Performance Analysis • the time to process a b byte packet is b/p+M+1 cycles where M is the number of matches found in the packet. b/p corresponds to the time for the packet to stream through the SMP signature matches and M + 1 is the time to do the matched address output.

  11. SMP Resource Utilization

  12. Comparison NIDS FPGA Designs

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