A CAM-based keyword match processor architecture

1. A CAM-based keyword match processor architecture Author: Long Bu, John A. Chandy * Publisher: Microelectronics Journal 37 (2006) Presenter: Han-Chen Chen Date:2009/11/18

2. Outline • Introduction • Architecture of Keyword match processor • Performance

3. Introduction • Pattern match : • Software algorithms : slow • FPGA Base : must be reconfigured when change keyword sets • CAM Base : reliance on fixed size keys. • Presents a cellular automata based design that is more space efficient and can easily handle arbitrarily sized keywords .The architecture is flexible enough to allow for ‘approximate word’ matches as well.

4. Introduction

5. Architecture of Keyword match processor

6. Architecture of Keyword match processor CAM and PE array Motomura: 4 match signals form the CAM array in a 5*3 PE array, a n-colume CAM array requires 5n/4*3 PE array =>Waste space

7. Architecture of Keyword match processor 1.if Mt(i) = 1 and PEt (i, j) = 1 then PEt+1 (i+1, j) = 1 PEt+1 (i, j+1) = 1 2.if Mt(i) ≠ 1 and PEt (i, j) = 1 then PEt+1 (i+1, j+1)=1 PEt+1 (i, j+1)=1 3.for (1 ≥ d ≤ D-j ) PEt (i+d, j+d)=1 Overall: PEt+1 (i, j)= PEt (i, j-1) + PEt (i-1, j) ∙Mt(i-1) + PEt (i-1, j-1) ∙Mt(i-1) + PEt+1 (i-1, j-1)

8. Architecture of Keyword match processor rule 1 rule 2 rule 3 Input: CONE Cycle1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Match signal

9. Architecture of Keyword match processor rule 1 rule 2 rule 3 Cycle2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 C 0 1 0 0 0 0 0 0 0 0 0 0 0 0 Match signal

10. Architecture of Keyword match processor rule 1 rule 2 rule 3 Cycle3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 O 0 0 1 0 0 0 0 0 0 0 0 0 0 0 Match signal

11. Architecture of Keyword match processor rule 1 rule 2 rule 3 Cycle4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 N 0 0 0 1 1 0 0 0 0 0 0 0 0 0 Match signal

12. Architecture of Keyword match processor rule 1 rule 2 rule 3 Cycle5 0 1 2 3 4 5 6 7 8 9 10 11 12 13 E 0 0 0 0 0 0 0 0 0 0 0 1 0 0 Match signal

13. Architecture of Keyword match processor rule 1 rule 2 rule 3 Cycle6 0 1 2 3 4 5 6 7 8 9 10 11 12 13 \0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 Match signal Match distance=2 Unmatch

14. Architecture of Keyword match processor Distance decoder: WM(i) = END∙M(i)∙(PE(i, 0)+PE(i, 1)+…+PE(i, D)) Match position finder: Find the previous word end Output Match Position array (size n) M(i) array PE match array Word Match array

15. Architecture of Keyword match processor Matched address output (MAO) logic • Binary tree priority encoder structure • To generate the matched address available All need : p+q+2 cycles p: length of input stream ,q match times , 2 initial & process distance flags

16. Architecture of Keyword match processor Keyword match processor with no delimiters: add E(i) array 1:last character 0:otherwise Subsequence keyword match: 1.if Mt(i) = 1 and PEt (i, j) = 1 PEt+1 (i, j+1) = 1 if(E(i) ≠ 1) PEt+1 (i+1, j) = 1 2.if Mt(i) ≠ 1 and PEt (i, j) = 1 PEt+1 (i, j+1)=1 if(E(i) ≠ 1) PEt+1 (i+1, j+1)=1 3.for (1 ≥ d ≤ D-j ) if(E(i+d-1) ≠ 1) PEt (i+d, j+d)=1 4.PEt (0,0)=1 if(E(i) = 1) PEt (i+1, 0)=1

17. Performance • 0.5μm 3-metal layer process: • tCLK>tDD+tDD2MPF+tMPF =>tCLK>7.66 ns. leads to a maximum clock frequency of 130.5 MHz.Taking into account the setup times and propagation times of the registers, we have been able to comfortably run the circuit at 100 MHz. equal to 800Mb/s . • 0.1μm 3-metal layer process: • 500MHZ , 4Gb/s

18. Thanks for your listening