Performed by: Yael Grossman & Arik Krantz Instructor: Mony Orbach

1. Technion - Israel institute of technology department of Electrical Engineering הטכניון - מכון טכנולוגי לישראלהפקולטה להנדסת חשמל High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות דו”ח סיכום פרויקט – חלק א' Design and Implementation of PCI-Express Switch Performed by:Yael Grossman & Arik Krantz Instructor:Mony Orbach סמסטר חורף 2006 1

2. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Abstract Design and implementation of a three-port switch based on the PCI-Express protocol, supporting transfer speeds of up to 2.5Gb/s. Implementation of error-checking (CRC) and algorithm to ensure in-order packet arrival. The project will be implemented in VHDL on an FPGA Virtex-II Pro platform. 2

3. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות System description The system is comprised of three independent ports. Each port receives and processes data packets individually, performing error-checks and extracting the routing information. The routing mechanism will transfer packets from port to port. When a packet is routed to another port, it is the port’s responsibility to ensure that it is transferred in the correct order on the outgoing port. It does this using two send queues. In addition, an packet acknowledge system is implemented, in which an ACK packet is sent out every time a valid packet arrives, and a NACK – if the packet is corrupted and needs to be re-transmitted. 3

4. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Specifications • Design must support high transfer rates – 2.5Gbit/sec, full-duplex, per port. • Support simultaneous connections on all ports. • Support complex real-time algorithms for: • Packet routing between ports • Error checking (CRC) and retransmission in case of error • Packet arbitration and prioritization according to type (data / control) • Hardware Platform: MEMEC V2P30 FF1152, using Xilinx XC2VP30 Virtex-II Pro FPGA. 4

5. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות System Block Diagram • Multi-Gigabit Transceiver (MGT) Handles high speed transmission and reception of packets.. • Receive Block RAM (BRAM) Stores received packets on arrival to the switch. • CRC Check Checks if the packet arrived without errors. • ACK/NACK Generator Creates a DLL packet which indicates to the sending device whether the packet arrived intact. • ACK/NACK Queue (ACKQ) Stores the generated DLLPs while they await sending. • Routing Block Decides on which outgoing port to forward the packet, according to lookup tables it contains. • Replay Buffer Contains all the packets that have been sent on the outgoing queue and have not yet received an ACK. • Send Queue 1 and 2 (SQ) Contain packets routed to current port from the other two switch ports. • Arbiter Decides which packet to transmit on the outgoing lane. 5

6. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות FPGA Block Diagram - Receive Data is received on the incoming queue, checked for errors (CRC) and then handled according to type (Data Packet- TLP, Control Packet – DLLP) 6

7. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות FPGA Block Diagram - Send After a data packet has been routed to its destination, the arbiter must choose which packet should be transmitted at any given time. 6