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Technion - Israel institute of technology department of Electrical Engineering. הטכניון - מכון טכנולוגי לישראל הפקולטה להנדסת חשמל. High speed digital systems laboratory. המעבדה למערכות ספרתיות מהירות. Project Characterization Subject:. Jitter Generator. Performed by: Oron Port

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Presentation Transcript
slide1

Technion - Israel institute of technology

department of Electrical Engineering

הטכניון - מכון טכנולוגי לישראלהפקולטה להנדסת חשמל

High speed digital systems laboratory

המעבדה למערכות ספרתיות מהירות

Project Characterization

Subject:

Jitter Generator

Performed by: Oron Port

Instructor: Mony Orbach

Winter 2006/7

1

project definition

High speed digital systems laboratory

המעבדה למערכות ספרתיות מהירות

Project Definition
  • Extension of the project “Jitter experiment”, performed by Gregory Zabolotov during Spring 2005 semester.
  • Developing GUI-based software for an easy user control of the deterministic jitter applied on a fed clock.

2

what is jitter

High speed digital systems laboratory

המעבדה למערכות ספרתיות מהירות

What is Jitter?

Jitter is the short term variation of the significant instants of a digital signal from their ideal positions in time.

5

existing hardware

High speed digital systems laboratory

המעבדה למערכות ספרתיות מהירות

Existing Hardware

Extension slot

PDC

Jitter Generator (JG) PCB

Vertex II Pro board

Hardware developed for the Vertex II Pro board extension slot. Using a Programmable Delay Chip (PDC), it is possible to define a delay between 2.2nsec and 12.2nsec (in 10psec increments) for a given clock signal. Changing the delay continuously and periodically creates a deterministic periodic jitter effect.

The JG board is connected to the SOPC data bus.

3

project implementation

High speed digital systems laboratory

המעבדה למערכות ספרתיות מהירות

Project Implementation

Vertex II Pro

board

Jitter Gen.

SOPC

RS-232

Data

Bus

E x t e n s i o n s l o t

Interface #1:

MMI – Man-Machine-Interface

GUI – Graphical-User-Interface

5

project implementation1

High speed digital systems laboratory

המעבדה למערכות ספרתיות מהירות

Project Implementation

Vertex II Pro

board

Jitter Gen.

SOPC

RS-232

E x t e n s i o n s l o t

Data

Bus

Interface #2:

RS-232 communication (Ethernet is optional)  * Transferring a jitter period’s data selected in interface #1 to the SOPC’s memory, and other commands according to what was selected.

5

project implementation2

High speed digital systems laboratory

המעבדה למערכות ספרתיות מהירות

Project Implementation

Vertex II Pro

board

Jitter Gen.

SOPC

RS-232

E x t e n s i o n s l o t

Data

Bus

Interface #3:

SOPC Data bus  Updating the PDC on the JG board with the current delay time, according the tables filled in the SOPC’s memory during interface #2.

5

specification

High speed digital systems laboratory

המעבדה למערכות ספרתיות מהירות

Specification
  • Hardware
    • Clock is provided differentially to the JG board using two SMA connectors. Jittered output from the JG board is the same.
  • Software
    • Will be developed in Visual C++ .NET GUI.
    • Will have the capability to choose either built-in jitter period (already defined in the SOPC) or dynamically upload a jitter period to the SOPC’s memory (10 typed of signals).

4

time table

High speed digital systems laboratory

המעבדה למערכות ספרתיות מהירות

Time Table

6

time table1

High speed digital systems laboratory

המעבדה למערכות ספרתיות מהירות

Time Table

6