Test of LLRF at SPARC

1. Test of LLRF at SPARC TIARA Final Meeting Marco Bellaveglia INFN – LNF Reporting for: Design and realization in PSIT. Schilcher, Andreas Hauff, Roger Kalt and LLRF section staff Design, installation and tests in LNFS. Gallo, M. Bellaveglia and RF group staff

2. Summary • Design and realization of the C band LLRF system at PSI • System description and specifications • Analogue sub-system description • Digital sub-system description • Measurements on the system at PSI • Tests at INFN-LNF • Installation in the SPARC tunnel • Measurements on the system at LNF • Next future - System online for structure conditioning • Next year - Integration in the SPARC control system • Conclusion TIARA Final Meeting

3. System description TIARA Final Meeting • The system will interface a RF high power system • 1 klystron • 1 RF pulse compressor (SLED) • 2 accelerating structures

4. System specifications • Analogue part • Number of RF signal receivers: 12 + 4 spares • RF Frequency 5.712 GHz • IF Frequency 39.666 MHz • Bandwidth (3dB) ±18 MHz • Phase resolution < 15 fs or 0.03 deg • Amplitude error ≈ 0.1 dB (10 dB range) • Digital part • 16 ADC channels (to sample IF waveforms) • 4 DAC channels (for vector modulator control) • FPGA for signal processing • EPICS server implemented in the main CPU TIARA Final Meeting

5. Analogue sub-system • Main components: • Vector modulator • RF frontend(receiver) • LO, IF and samplingclock frequencygenerator TIARA Final Meeting

6. Analogue sub-systemVector modulator • Differential I/Q inputs DC - 20 MHz bandwidth (3dB) • Integrated RF switches for interlock: 76 dB suppressionand 1us switching time TIARA Final Meeting

7. Analogue sub-systemVector modulator TIARA Final Meeting Integrate time jitter (from 10Hz to 10MHz) is 22 fs RMSNo significant jitter added to the reference oscillator Output spectrum for a 1MHZ offset and19MHz offset frequency generated

8. Analogue sub-systemRF receiver board down-converter channels (16) RF shielding Power supplyfilter TIARA Final Meeting RF inputs (16)

9. Analogue sub-systemLO generator TIARA Final Meeting It generates the 5712+39.666MHZ LO frequency for the down-conversion of the RF signals to the IF

10. Analogue sub-systemFrequency divider TIARA Final Meeting • It generates all the frequencies needed by the system • IF, ADC clock, DAC clock • Time jitter is about 100fs RMS

11. Digital sub-system • Main components: • ADCs and DAC data communication • Digital signal processing • Control system interface TIARA Final Meeting

12. Digital sub-system - Layout TIARA Final Meeting MASTER SLAVE

13. Digital sub-systemADCs and DAC TIARA Final Meeting • ADC card • FMC516 from Curtiss-Wright • 4ch / 16bit / 250Msps / AC-coupled • Read IF waveforms • 3 cards required for 12x ADC channel + 1 spare • DAC card • FMC204 from 4DSP • 4-Channels / 16-bit / 1Gsps / AC coupled • Convert 4ch AC coupled to 2ch DC-coupled differential • Controls the vector modulator

14. Digital sub-systemFPGA and RT application • FPGA • RF signal processing • Interfaces ADCs and DAC • Write data on local memory • RT application • Data processing • Read data from local memory • Computes averages, standard deviations and jitters • Communication with EPICS • Receive and handle inputs from epics • Send raw and processed ADC channel data to epics TIARA Final Meeting

15. Digital sub-systemGUI software • Provided by PSI • Programmed in QT environment • It can read and write most of the EPICS variables • LLRF control is possible at SPARC at least in first operations TIARA Final Meeting

16. Measurements at PSI • ADC IQ measured 3dB bandwidth (from IF): ±18MHz • 180° phase jump performed in about 25ns (measured by 40Gs/s scope) • Intra-pulsestandard deviations: • LO Amplitude: 3.6 e-4 (relative) • LO Phase: 0.021° • VM Amplitde: 1.09 e-3 (relative) • VM phase: 0.13° TIARA Final Meeting

17. Tests at LNFInstallation in the SPARC tunnel TIARA Final Meeting FRONT BACK

18. Tests at LNFVector modulator phase measurement TIARA Final Meeting • Phase measured by two ADC channels just after system installation • Vector modulator drift observed • System at regime in about 1h • In any case the drift can be compensated with feedback • Subtraction of the phase measured from the two channels • Relative error on absolute phase in the two channel is • 0.015° RMS, considering the thermal drift • 0.011° RMS at regime

19. Tests at LNFVector modulator amplitude and phase avg. • Measured values meet the specifications • Vector modulator seems to perform better than in PSI • The DAC card has been substituted because it was not functioning after the shipping at LNF. Maybe the card had worse performance because it was starting to malfunction in PSI • We also are using a dedicated RF oscillator and not a frequency synthesizer TIARA Final Meeting

20. Tests at LNF - 180° phase jump TIARA Final Meeting • Any shape of the vector modulator output waveform in amplitude and phase is possible • 180° phase jump performed • System ready to feed pulse RF compressor

21. Next future – first power testsConditioning of the 2nd section • The system will be used only to read the signals from cavity, maintaining the temporary LLRF system in use for a first test phase 5712MHz Ref signal Temporary LLRF Acc. structure TIARA Final Meeting

22. Next future - Full capability testConditioning of the 2nd section • The system will be used in the conditioning both to drive the klystron and to read the signal from the power RF network • System will be fully commissioned 5712MHz Ref signal Temporary LLRF Acc. structure TIARA Final Meeting

23. Integration in the SPARC control system TIARA Final Meeting • QT GUI provided by PSI and custom LabVIEW GUI running at the same time • We can read/write every EPICS variable • System ready to be integrated in the SPARC control system

24. Integration strategy RF cabling EPICS RF power system PSI LLRF Frontend CPU w LabVIEW Ethernet Serial, USB, firewire, … Other linac device Frontend CPU w LabVIEW Ethernet TIARA Final Meeting Serial, USB, firewire, … Other linac device Frontend CPU wLabVIEW Ethernet

25. Integration strategy RF cabling EPICS RF power system PSI LLRF Frontend CPU w LabVIEW Ethernet One layer added to the CS architecture Serial, USB, firewire, … Other linac device Frontend CPU w LabVIEW Ethernet TIARA Final Meeting Serial, USB, firewire, … Other linac device Frontend CPU wLabVIEW Ethernet

26. Integration strategy RF cabling EPICS RF power system PSI LLRF Frontend CPU w LabVIEW Ethernet Standard RF frontend application is to be modified to include the EPICS/LabVIEW interface Serial, USB, firewire, … Other linac device Frontend CPU w LabVIEW Ethernet TIARA Final Meeting Serial, USB, firewire, … Other linac device Frontend CPU wLabVIEW Ethernet

27. Done • December 2013 • 2014 Conclusion • Design and realization at PSI • Measurements on simulated signalsat PSI show that specifications are met • Shipping to LNF (substitution of the broken DAC card) • Measurements on simulated signal at LNF show that specifications are met • EPICS/LabVIEW interface drivers provide full control of LLRF • Test the system on real signals from RF power system • Conditioning of the second TW accelerating section using LLRF from PSI • Full integration in the SPARC control system TIARA Final Meeting