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Chapter 2. Logic Circuits. Variables and Functions. x. =. 0. x. =. 1. (a) Two states of a switch. S. x. (b) Symbol for a switch. Figure 2.1. A binary switch. A closed circuit. S. Battery. Light. x. (a) Simple connection to a battery. S. Power. Light. x. supply.

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chapter 2

Chapter 2.

Logic Circuits

slide2

Variables and Functions

x

=

0

x

=

1

(a) Two states of a switch

S

x

(b) Symbol for a switch

Figure 2.1. A binary switch.

slide3

A closed circuit

S

Battery

Light

x

(a) Simple connection to a battery

S

Power

Light

x

supply

(b) Using a ground connection as the return path

Figure 2.2. A light controlled by a switch.

slide4

AND and OR logic functions

S

S

Power

x1

x2

Light

supply

(a) The logical AND function (series connection)

S

x1

Power

Light

supply

S

x2

(b) The logical OR function (parallel connection)

Figure 2.3. Two basic functions.

slide5

S

X1

S

Power

Light

X3

supply

S

X2

Figure 2.4. A series-parallel connection.

slide6

Truth Table for two input variables

Figure 2.6. A truth table for the AND and OR operations.

slide7

Truth Table for three input variables

Figure 2.7. Three-input AND and OR operations.

slide8

x

AND, OR and NOT gates

1

x

2

x

1

×

×

¼

×

x

x

x

×

x

x

1

2

n

1

2

x

2

x

n

(a) AND gates

x

1

x

2

x

1

¼

x

+

x

x

+

x

+

+

x

1

2

1

2

n

x

2

x

n

(b) OR gates

x

x

(c) NOT gate

Figure 2.8. The basic gates.

slide9

A logic Circuit

x

1

x

2

(

)

.

f

=

x

+

x

x

1

2

3

x

3

Figure 2.9. The function from Figure 2.4.

boolean algebra
Boolean Algebra

Definition:Boolean Algebra: A mathematical system for formulating logical statements with symbols so that problems can be solved in a manner similar to ordinary algebra. In short, Boolean algebra is the mathematics of digital systems. The basic rules for Boolean addition and multiplication are presented in Table 1-9.

Axioms of Boolean Algebra

slide12
Laws of Boolean Algebra

Commutative Laws

  • The commutative law of addition for two variables is algebraically expressed as
  • x + y = y + x
  • The commutative law of multiplication for two variables is expressed as
  • xy = yx
  • In summary, the order in which the variables are ORed or ANDed make no difference.
slide13
Associative Laws
  • The associative law of addition of three variables is expressed as
  • x+ (y + z) = (x + y) + z
  • The associative law of multiplication of three variables is expressed as
  • x(yz) = (xy)z
  • In summary, ORing or ANDing a grouping of variables produces the same result regardless of the grouping of the variables.
slide14
Distributive Law
  • The distributive law of three variables is expressed as follows:
  • x (y+z) = xy + xz
  • This law states that ORing several variables and ANDing the result is equivalent of ANDing the single variable with each of the variables in the grouping, then ORing the result.
duality
Duality
  • To reflect the principle of duality, the axioms and single-variable theorems are listed in pairs.

For example, see 5a and 3a.

When x =0, by 5a, the result is 0.

When x =1, by 5a, the result is 0, which is also proved by 3a.

slide19
Boolean Simplification

Example1:

F = AB’ + C’D + AB’ + C’D

= AB’ + C’D (by identity 5)

Example2:

F = ABC + ABC’ + A’C

= AB(C + C’) + A’C (by identity 13)

= AB(1) + A’C (by identity 7)

= AB +A’C (by identity 4)

slide20

Logic circuit implementation

(Before simplification)

(After simplification)

demorgan s theorem
DeMorgan’s Theorem

(A B)’ = A’ + B’ (1)

That is, the complement of the product is equivalent to the sum of the complements.

This is true for any number of variables.

(A B C … Z)’ = A’ + B’ + C’ + …+ Z’

(A +B)’ = A’ B’ (2)

Similarly, the complement of the sum is equivalent to the product of the complements.

Similarly, (A + B + C + …+ Z)’ = A’ . B’ . C’ . … . Z’

slide22
Methods to complement a function:

Interchange 1’s and 0’s for the values of F in the truth table . Use DeMorgan’s theorem on algebraic function

  • Change F to F’, and F’ to F
  • Change OR to AND
  • Change AND to OR
  • Complement each individual variable

Example 1:

F = AB+ C’D + B’D

Applying DeMorgan’s theorem,

F’ = (A’ + B’)(C + D’)(B + D’)

slide23
Example 2:

Simplify F = (x1 + x3) . (x1’+ x3’)

F = x1 x1’+ x1 x3’ + x3 x1’+ x3 x3’ (Distributive Property)

x1 x1’ and x3 x3’ = 0 ( Identity 8)

F = x1 x3’ + x1’ x3

Example 3:

F = x’yz + x’yz’ +xz

= x’y(z + z’ ) + xz (Factoring out)

= x’y .1 + xz ( By Identity 6)

= x’y + xz ( By Identity 4)

slide24
Practice Problems:
  • Find the complement: (xyz)’
  • Expand: x + yz
  • Simplify: a) x’y’ +x’y + xy

b) x’y’ + xz + xy + yz’

c) wy + w’yz’ + wxy + w’xy’

slide25

Proof of DeMorgan’s theorem using truth table

Figure 2.11. Proof of DeMorgan’s theorem in 15a.

slide26
Boolean Functions

Example1:

Prove:

(A + B) (A’ + B’) = AB’ + A’B

LHS =AA’ +AB’ + BA’ + BB’ (by distributive property)

= 0 + AB’ +BA’ +0 = AB’ +A’B = RHS

Example2:

Prove:

AC’ +B’ C’ + AC + B’C = A’B’ +AB +AB’

LHS = A(C +C’) + B’(C+C’) = A.1 + B’.1 = A + B’

RHS = A’B’ +AB +AB’ = A’B’ + A(B + B’) = A’ B’ + A = A + B’ (by identity 11)

LHS = RHS

precedence of operations
Precedence of Operations

NOT, AND, and then OR

Example:

A.B + A’.B’

1. Complements

2. AND operation

3. OR operation

slide28

Synthesis using gates

F = m0 .1 + m1 . 1 + m2 .0 +m3 .1

Figure 2.15. A function to be synthesized.

slide29

x

1

x

2

f

(a) Canonical sum-of-products

x

1

f

x

2

(b) Minimal-cost realization

Figure 2.16. Two implementations of a function in Figure 2.15.

slide30

Sum of Products (SOP) and Product of Sums (POS)

Minterm: A product term with all ‘n’ variables in asserted or negated form.

Maxterm: Complement of a minterm.

Figure 2.17 Three-variable minterms and maxterms.

slide31

Terms and Definitions:

Minterm: A product term with all ‘n’ variables in asserted or negated form.

Maxterm: Complement of a minterm.

Sum-of-products (SOP).

Product-of-sums (POS).

Canonical sum-of-products.

Canonical product-of-sums.

Analysis - The task of determining the function performed by a system

Synthesis - is the reverse task of analysis, and is defiend as the designing of a new system that implements a desired functional behavior.

slide32

Figure 2.18. A three-variable function.

f = x1’ x2’x3 + x1 x2’ x3’ + x1 x2’ x3 + x1 x2 x3’

f( x1, x2, x3) = ∑(m1 m4, m5, m6) = ∑ m(1, 4, 5, 6)

f ’ = x1’ x2’ x3‘+ x1‘x2 x3’ + x1‘x2 x3 + x1x2 x3

f = (x1+ x2 + x3) ( x1+x2‘ +x3) (x1 + x2‘+ x3‘) (x1‘ + x2‘ + x3‘)

f( x1, x2, x3) = ∏(m0 m2, m3, m7= ∏ m(0, 2, 3, 7)

slide33

x

2

f

x

3

x

1

(a) A minimal sum-of-products realization

1

x

3

f

x

2

f = x1’ x2’x3 + x1 x2’ x3’ + x1 . x2’ . x3 . + x1 x2 x3’

= x2’x3 (x1 + x1‘) + x1x3‘(x2 + x2‘) = x2’x3 + x1x3‘

f = (x1 +x3) (x2’ + x3‘)

(b) A minimal product-of-sums realization

Figure 2.19. Two realizations of a function in Figure 2.18.

slide34

Example 2.3. f( x1, x2, x3) = ∑ m (2, 3, 4, 6,7)

Simplify the function and draw the circuit (synthesis).

Steps:

1. Write the canonical sop expression

2. Simplify the function.

3. Draw the circuit.

4. Calculate the cost - Count the number of gates together with input line sto those gates and express as CUs.

Example 2.4. Express the function in Example 1 as a POS, repeat the steps and draw the circuit.

Example 2.5. f( x1, x2, x3, x4 ) = ∑ m (3,7,9,12,13,14,15)

slide35

Section 2.7 NAND and NOR Logic Networks

Figure 2.20. NAND and NOR gates.

slide36

NAND and INVERT-OR Equivalency and

NOR and INVERT-AND Equivalency

x

1

x

x

1

1

x

x

2

2

x

2

x

x

x

x

=

+

(a)

1

2

1

2

x

1

x

x

1

1

x

x

2

2

x

2

x

x

x

x

+

=

(b)

1

2

1

2

Figure 2.21. DeMorgan’s theorem in terms of logic gates.

slide37

x

x

1

1

x

x

2

2

x

x

3

3

x

x

4

4

x

x

5

5

x

1

x

2

x

3

x

4

x

5

SOP - AND-OR and All NAND implementations

Figure 2.22. Using NAND gates to implement a sum-of-products.

slide38

x

x

1

1

x

x

2

2

x

x

3

3

x

x

4

4

x

x

5

5

x

1

x

2

x

3

x

4

x

5

POS - OR-AND and All NOR implementations

Figure 2.23. Using NOR gates to implement a product-of sums.

slide39

x1

x2

f

x3

(a) POS implementation

x1

x2

f

x3

(b) NOR implementation

Figure 2.24 NOR-gate realization of the function in Examples 2.4. and 2.6

slide40

x1

f

x2

x3

(a) SOP implementation

x1

f

x2

x3

(b) NAND implementation

Figure 2.25. NAND-gate realization of the function in Examples 2.3. and 2.7