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EKV Compact Model Extension for High-Voltage Lateral DMOS Transistors

EKV Compact Model Extension for High-Voltage Lateral DMOS Transistors. N. Hefyene (1) C. Anghel (1) J.M. Sallese (1) A.M. Ionescu (1). (1) EPFL, Lausanne, Switzerland Contact: naser.hefyene@epfl.ch. Outline. · Investigated HV devices · Intrinsic-Drain voltage concept

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EKV Compact Model Extension for High-Voltage Lateral DMOS Transistors

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  1. EKV Compact Model Extension for High-Voltage Lateral DMOS Transistors N. Hefyene (1) C. Anghel (1) J.M. Sallese (1) A.M. Ionescu (1) (1) EPFL, Lausanne, Switzerland Contact: naser.hefyene@epfl.ch

  2. Outline ·Investigated HV devices ·Intrinsic-Drain voltage concept ·MESDRIFT structure ·Drift resistance modeling ·EKV Model extension to HV DMOS transistors · Model Parameter · Model vs. Measurements · Optimizing Strategy ·Advantages & Limitations ·Future Developements MOS-AK, 5th May 2003, Crolles, France 1

  3. INVETIGATED STRUCTURES EXtended lateral DMOS architecture (XDMOS) 0.7 m HV-CMOS technology from Alcatel Microelectronics (AMIS) K-point (VK) • n-channel transistor • Lch= 4mm •  not self-aligned Intrinsic channel Drift region MOS-AK, 5th May 2003, Crolles, France 2

  4. Systematic inspections of the K-point potential (VK) in all regimes of operation reveal… VK < 10V for: VG 12V VD 100V Numerical simulations of XDMOS architectures   VK (VG, VD) • INTRINSIC - DRAIN • VOLTAGE CONCEPT Intrinsic DMOS channel behaves like a low-voltage MOSFET à model the intrinsic DMOS channel with a standard low-voltage MOSFET model (like BSIM or EKV) • separately model the characteristics of the drift region MOS-AK, 5th May 2003, Crolles, France 3

  5. “Cross-sectional illustration” “Upper view” • MESDRIFT : a new test structure MESDRIFT structure : à n+-implant near the channel - drift region delimitation à high-impedance voltmeter to monitor the VK potential Features : • small dimensions of the K-contact compared to the global device width (10  200 m) àminor influences on the global device characteristics are expected MOS-AK, 5th May 2003, Crolles, France 4

  6. “ID (VG) @ # VD” “ID (VD) @ # VG” ( ) MESDRIFT vs. ( ) XDMOS • XDMOS vs. MESDRIFT : • DC characteristics (W = 40 m) • increased leakage currents in the sub-threshold region • slight shift in VDBR for the MESDRIFT test structure at low VG (<5%) • overall good match between XDMOS and MESDRIFT characteristics MOS-AK, 5th May 2003, Crolles, France 5

  7. “VK(VD) @ # VG” “RD(VD) @ # VG” • MESDRIFT : typical extracted • Drift characteristics VK potential evolution with external biases  as predicted by 2D numerical simulation • VKäVDä • VKæVGä Drift resistance evolution with external biases : RD = (VD – VK)  ID • in agreement with 2D numerical simulations (better at high VG , due to the formation of a drift accumulation layer beneath gate oxide) MOS-AK, 5th May 2003, Crolles, France 6

  8. Drift expression vs. measured RD (VD, VG) : p-channel DMOS n-channel DMOS ( ) Measured vs. ( ) modeled characteristics  • DRIFT RESISTANCE MODELING The proposed quasi-empirical drift expression… • rD0, rD1,  0, 1, 0, 2, 1 & 0  room temperature parameters (T0) • m and n temperature dependence parameters (T) Features :  limitednumber of parameters… 10! good accuracy over temperature… 25°C up to 150°C unique expression for different drain architectures (p- & n-channel XDMOS) MOS-AK, 5th May 2003, Crolles, France 7

  9. VG VD VS pMOS nMOS JFET VG Diodes VS Drift model VD nMOS VB      VB no of elements   no of device phenomena to be considered no of nodes circuit complexity    model complexity  • HV-DMOS MODELING Two possible approaches :  COMPACT - modeling… consider the device unity  Expression continuity in all regimes of operations  a set of self-consistent expressions able to predict and reproduce specific phenomena  MACRO - modeling… discrete elements tied together to form a circuit (e.g. MOSFET, JFET, diode, capacitor, Resistor… etc.) accuracy parameters no& extraction ► ► ► simulation time std. MOS + drift model parameters MOS-AK, 5th May 2003, Crolles, France 8

  10. MODELING WITH EKV Assumptions  long-channel approximation (i.e. short-channel effects are neglected)  eff(i.e. simplified mobility dependence on 2D field-effects) Simplified expression Complete expression Strong-Inversion Weak &Strong-Inversion Implicit expression Can only be solved Numerically Explicit expression (2nd order polynomial) Simple Analyticalsolutions MOS-AK, 5th May 2003, Crolles, France 9

  11. Strong Inversion expressions Quasi-empirical drift expression Charge expression: ,  Effective mobility: Current expressions:  Smoothing function (i.e. linear to saturation transition)  Total current expression MOS-AK, 5th May 2003, Crolles, France 10

  12. MODEL PARAMETER: MOS-AK, 5th May 2003, Crolles, France 11

  13. ( ) Measured vs. ( ) modeled characteristics  • COMPACT- MODEL vs. MEASURES :  Fitted on a standard 4 m n-channel XDMOS device, using the simplified drain expression. ID-VD characteristics (TR) gD(VD) @ # VG ID(VD) @ # VG For ID(VD) curves MOS-AK, 5th May 2003, Crolles, France 12

  14. gm(VG) @ # VD ID(VG) @ # VD ( ) Measured vs. ( ) modeled characteristics  ID-VG characteristics (TR) For ID(VG) curves ** Errors calculated for G  3V MOS-AK, 5th May 2003, Crolles, France 13

  15. n-channel DMOS depend on known quantities (i.e. VG, VD and measured ID) ( ) Extracted (calculated) with RD(VG, VD, T) ( ) Measured on MESDRIFT structure  • GLOBAL OPTIMIZING STRATEGY  simplified ID formula ►►explicit expression ►►  since: “Rdrift(VD) @ # VG” MOS-AK, 5th May 2003, Crolles, France 14

  16. The modelling strategy can be sequenced as follows: (i)  Performing standard extrinsic I-V measurements on the HV DMOS transistor; (ii) Extracting VT and 0 parameters; (iii) Calculating drift resistance characteristics according to : ; (iv) Fitting, with the quasi-empirical drift expression the calculated drift- resistance in (iii); (v) Injecting the drift parameters, together with the extracted VT and 0 values, in the simplified drain current expression + optimisation of the set of injected parameters to fit the desired DC measured characteristics NOTE: In case weak and moderates inversions have to be modelled, optimised parameters from (v) can be used as initial guess values for the more complex implicit expression of the drain current. MOS-AK, 5th May 2003, Crolles, France 15

  17. ADVANTAGES & LIMITATIONS Model Advantages :  a total # of (8+4) parameters for room temperature model simpleandfast extraction of intrinsic MOS parameters (i.e. VT and 0)  a modeling strategy and an extraction procedure, independent on the MESDRIFT architecture  a charge based model; adequate and more convenient for AC modeling! Limitations :  limited accuracy in the weak inversion region (to be improved) MOS-AK, 5th May 2003, Crolles, France 16

  18. FUTURE DEVELOPEMENTS  including the temperature dependence for the intrinsic channel part (under development) Replacing the simplified EKV model by a more complete version (e.g. EKV 2.6) implementing model equations into simulator using Verilog-A code (under development)  AC-modeling with a charge based approach (under development)  complete model implementation into simulators (e.g. SPICE or SABER) Acknowledgements: This work was supported by the IST-1999-12257 ‘AUTOMACS' EC project and the Swiss OFES no. 00-0009. MOS-AK, 5th May 2003, Crolles, France 17

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