CMOS Analog Design Using All-region MOSFET Modeling

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## CMOS Analog Design Using All-region MOSFET Modeling

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**CMOS Analog Design Using All-region MOSFET Modeling**Chapter 4 Temporal and spatial fluctuations in MOSFETs CMOS Analog Design Using All-Region MOSFET Modeling**Noise and mismatch**The spontaneous fluctuations over time of the current and voltage inside a device, which are basically related to the discrete nature of electrical charge, are called electrical noise. Time-independent variations between identically designed devices in an integrated circuit due to the spatial fluctuations in the technological parameters and geometries are called mismatch. Mismatch (spatial fluctuation) and noise (temporal fluctuation) are similar phenomena, both depending on process, device dimensions, and bias. Mismatch can be seen as “dc noise”. CMOS Analog Design Using All-Region MOSFET Modeling**Types of noise: Thermal noise**(a) Norton and (b) Thevenin equivalent circuits of a real (noisy) resistor. The resistor in the equivalent circuits is an ideal (noiseless) resistor. Nyquist formulas k=1.38·10-23 J/K is the Boltzmann constant and f is the bandwidth in Hertz over which the noise is measured R G = 1/R (a) (b) + CMOS Analog Design Using All-Region MOSFET Modeling**Thermal noise calculation**On the other hand, the rms value of the thermal noise voltage per Hz1/2 is CMOS Analog Design Using All-Region MOSFET Modeling Calculate the rms (root mean square) value of the thermal noise current per Hz1/2 of a 1 mA/V conductance at T= 300 K.**Consistency of noise models**R1 R2 + + CMOS Analog Design Using All-Region MOSFET Modeling A noise model is consistent regarding series or parallel associations if the composition of the noise contributions from the individual series (or parallel) elements is the same as the noise from the series (or parallel) equivalent. The thermal noise model for a resistor given by is consistent The total noise voltage introduced into the circuit can be obtained by composing the individual noise sources or using Nyquist formula to calculate the noise of the equivalent resistor Req=R1+R2.**Shot noise (vacuum tubes, diodes, and bipolar transistors)**The rms value of the shot noise per Hz1/2 in a p-n junction diode for a 1 A dc current is CMOS Analog Design Using All-Region MOSFET Modeling Shot noise is associated with the random flow of carriers across a potential barrier. The fluctuation of a current I around its average value IDC Shot noise is given by the Schottky formula as q is the electronic charge and f is the bandwidth in Hertz**Flicker (1/f)noise**All active devices, and some passive devices such as carbon resistors, present excess noise at low frequencies, which is called flicker noise. Flicker noise occurs when a direct current is flowing: flicker noise can be regarded as produced by a fluctuation in conductance. The power spectral density of flicker noise varies with frequency in the form with K and EF being constants. Since in most cases EF1, flicker noise is also called 1/f noise. CMOS Analog Design Using All-Region MOSFET Modeling**Calculation of flicker noise**CMOS Analog Design Using All-Region MOSFET Modeling Assume that EF = 1 and K=10-20 A2. Calculate the mean square value of the flicker noise current over a frequency range of (a) [10 Hz, 10 kHz]; (b) [10 Hz, 10 MHz]; (c) [(1 (million year)-1, 1 year-1] which leads to the following results a) b) c)**Modeling drain current fluctuations - 1**Channel splitting Transistor equivalent circuit Mu: W/(L-y) R Ml: W/y VD VG L-y A y L y W CMOS Analog Design Using All-Region MOSFET Modeling**Modeling drain current fluctuations - 2**Current division CMOS Analog Design Using All-Region MOSFET Modeling**MOSFET thermal noise**CMOS Analog Design Using All-Region MOSFET Modeling Conductance of a MOSFET channel element Mean-square thermal noise of the channel element Nyquist Mean-square value of the total drain current fluctuation**Thermal noise excess factor - 1**CMOS Analog Design Using All-Region MOSFET Modeling For VDS0, the transistor is equivalent to a resistor and where gms (=gmd) is the equivalent conductance of the transistor In weak inversion For a saturated transistor (gms>>gmd) in weak inversion**Thermal noise excess factor - 2**CMOS Analog Design Using All-Region MOSFET Modeling In general, the channel thermal noise is written as • is named the excess noise factor and its value is 2/3 for a long-channel saturated transistor in strong inversion. For a short channel transistor Le and Lesat are the electrical channel length in the linear and the saturation regions, respectively. Considering that Lesat= Le-L, where L is the channel shortening due to CLM, then for short channel transistors it is possible that >1 due to the CLM effect.**Flicker noise in MOSFETs**Spectral density of a simulated waveform obtained superimposing many random telegraph signals with single time constants having values generated according to CMOS Analog Design Using All-Region MOSFET Modeling**Flicker (1/f) noise model**As for thermal noise, we calculate the mean-square value of the total drain current fluctuation from the local current fluctuation in the channel : effective number of traps/area In terms of inversion levels CMOS Analog Design Using All-Region MOSFET Modeling**Dependence of the 1/f noise on bias**CMOS Analog Design Using All-Region MOSFET Modeling**Normalized flicker and thermal PSD at f=1kHz for saturated**NMOS-T (W/L=200/5) Thermal and 1/f noise 1E-9 7 -2 (N =2.6x10 cm ) ot 1E-10 1E-11 2 1E-12 D 1/f Noise /I ID S (a) Simulated Thermal Noise 1E-13 (b) Simulated Simulated (Typ.NMOS model) measured 1E-14 measured 1E-15 10n 100n 1µ 10µ 100µ 1m 10m [A] Drain Current CMOS Analog Design Using All-Region MOSFET Modeling**Corner frequency**Noise corner frequency (frequency at which the PSD of the 1/f noise equals the PSD of the thermal noise) can be expressed in terms of MOSFET transition frequency CMOS Analog Design Using All-Region MOSFET Modeling**Systematic and random mismatch**CMOS Analog Design Using All-Region MOSFET Modeling Mismatch is the name given to the time-independent differences between identically designed and identically used devices. The performance of most analog, or even digital, circuits relies on the concept of matched behavior between identically designed and used devices. In analog circuits, unwanted differences in the effective value of equally designed components, such as threshold voltage differences of millivolts or less, can critically reduce the performance and/or yield of a circuit. Even for digital circuits, transistor mismatch can lead to propagation delay differences in clock trees, reducing the robustness of the circuit. The shrinkage of the MOSFET dimensions and the reduction in the supply voltage make matching limitations even more important.**Global manufacturing variations**GLOBAL variation total variation of a parameter over a chip, a wafer (a batch) caused by equipment variations & spatial drift, e. g. Dimensional errors (photo-mask sizes, lens aberrations) Photo-resist thickness variations Mechanical strain variation Because GLOBAL variations are correlated across die, they are minimized by design tricks: common centroid components distance reduction between identically designed pairs same orientation, etc. CMOS Analog Design Using All-Region MOSFET Modeling**Random local variations**LOCAL variation variation in a component with respect to an identical adjacent component, caused by atomistic stochastic effects ion implantation, dopant diffusion and clustering Interface states, fixed charges edge roughness, poly-Si grain effects Simulation: generate random mismatch that depends on dimensions, process parameters, and bias. Designers must understand the limitations imposed by LOCAL variations on performance. CMOS Analog Design Using All-Region MOSFET Modeling**Pelgrom’s model of mismatch - 1**W source L xd drain CMOS Analog Design Using All-Region MOSFET Modeling number of atoms per unit volume in silicon is NSi=5·1022 cm-3 probability p of having an acceptor atom in the place of a silicon atom number N of crystal atoms in the depletion region under the gate fluctuation in the number of acceptor atoms under the gate of an n-channel transistor (binomial distribution) since p<<1(Poisson distribution)**Pelgrom’s model of mismatch - 2**CMOS Analog Design Using All-Region MOSFET Modeling In most applications: standard deviation of the difference between the threshold voltages of two identical transistors (VT0=VT1-VT2)**Pelgrom’s model of mismatch - 3**The standard deviation of the n-channel MOSFET threshold voltage vs. the inverse square root of the gate area for a .18 m process CMOS Analog Design Using All-Region MOSFET Modeling**VTO matching coefficient vs. process**The threshold-voltage matching coefficient over process generations CMOS Analog Design Using All-Region MOSFET Modeling**Number fluctuation mismatch model - 1**inversion charge y depletion charge y 0 VGB p-substrate Cross section of an MOS transistor showing the (greatly exaggerated) fluctuations in both inversion and depletion charge densities due to local dopant fluctuations CMOS Analog Design Using All-Region MOSFET Modeling**Number fluctuation mismatch model - 2**• Assumptions and/or approximations: • The capacitive model of the MOS transistor, assuming the depletion capacitance to be dependent on the gate voltage only and the inversion capacitance to be proportional to the inversion charge density; • The fluctuation of the impurity concentration in the depletion layer as the main source of mismatch; • Poisson distribution of impurity atoms; • Uncorrelated local impurity fluctuations; Noi: effective number of impurities per unit area of gate CMOS Analog Design Using All-Region MOSFET Modeling**Mismatch dependence on inversion level - 1**In terms of inversion levels where _______________________ For long channel MOSFET CMOS Analog Design Using All-Region MOSFET Modeling**Mismatch dependence on inversion level - 2**CMOS Analog Design Using All-Region MOSFET Modeling**Mismatch model including IS fluctuations**One can include the random errors due to the specific sheet current AISH is the parameter which accounts for mismatch in ISH. For high inversion levels, mismatch levels out at a minimum value determined by AISH AISH values are of the order of 1 %-m CMOS Analog Design Using All-Region MOSFET Modeling**Mismatch: Experimental results – 1**VG VD IB ID MREF Mi VB Saturation level dependence Measured: —; Model: --- Test chip: 24 NMOS transistors (W=30m, L= 1.2m)in the ES2 1.2m CMOS DLM process CMOS Analog Design Using All-Region MOSFET Modeling Test circuit**Mismatch: Experimental results – 2**Dependence on inversion level Linear: (VDS=50mV); Saturation: (VDS=1V) regions. —; Model CMOS Analog Design Using All-Region MOSFET Modeling