1 / 15

Overview

This overview discusses the need for a new design methodology for Globally Asynchronous, Locally Synchronous (GALS) systems and introduces an optimized integrated Quadrature Voltage-Controlled Oscillator (QVCO) for clock generation. The design strategy, simulations, and layout are presented, along with performance and power consumption considerations. The QVCO is designed using a prototype Gm-LC VCO with I-MOS varactors, achieving a tuning range of 10% and worst-case phase noise of -190 dBc/Hz. Future work includes incorporating the QVCO into a PLL design and completing other clock generator modules.

bennettkatz
Download Presentation

Overview

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. An Optimized Integrated QVCO for Use in a Clock Generator for a NewGlobally Asynchronous, Locally Synchronous (GALS) Design Methodology.

  2. Overview • Background • Need for this new design methodology. • Why GALS? • What is novel in this design? • Need for QVCO • Design Strategy • Simulations & Layout • Conclusion

  3. Multiplier cos wu sin wt CDA Phase Locked Loop Dual Sample & Hold Clock sin w(t-u) cos wt sin wu Multiplier Run SRFF1 SRFF2 Init1! Done! Init2! CLOCK GENERATOR Ref [1]

  4. Simple Phase Locked Loop Source: http://www.uoguelph.ca/~antoon/gadgets/pll/pll.html

  5. VCO Core Design Ref [4]

  6. SIOS (Spiral Inductor On Silicon) Design Spiral Inductor Parameters Ref [6], [8]

  7. Inversion Mode (I-MOS) Varactor Design Ref [9]

  8. Quadrature Generation Ref [12], [13]

  9. QVCO Simulation Summary

  10. QVCO Performance Summary

  11. QVCO Full Custom Layout

  12. Conclusion • A good compromise between area and overall power consumption was achieved. • A prototype quadrature –Gm LC-VCO for 650 MHz was designed in standard 0.25 µm, single-poly, five-metal, 2.5 V CMOS technology. • A tuning range of 10% was obtained through the use of I-MOS varactors.

  13. Conclusion (Contd.) • SIOS achieving a Q of 5 were also created. • Simulated worst-case phase noise is -190 dBc/Hz at 600 MHz. • Occupies an area of 800 µm X 300 µm (0.24 mm2). • The designed VCO dissipates only 21 mW and operates from a single 2.5 V supply voltage.

  14. Future Work • Incorporate QVCO into PLL Design. • Complete other Clock Generator Modules.

  15. An Optimized Integrated QVCO for Use in a Clock Generator for a New Globally Asynchronous, Locally Synchronous (GALS) Design Methodology.

More Related