digital testing scan design n.
Download
Skip this Video
Loading SlideShow in 5 Seconds..
Digital Testing: Scan Design PowerPoint Presentation
Download Presentation
Digital Testing: Scan Design

Loading in 2 Seconds...

play fullscreen
1 / 38

Digital Testing: Scan Design - PowerPoint PPT Presentation


  • 906 Views
  • Uploaded on

Digital Testing: Scan Design. Samiha Mourad Santa Clara University. Outline. Problems with sequential testing What is scan Types of scan Types of storage devices Scan Architectures Cost of Scan Partial Scan Stitching flip-flops. Problems Impeding Testing.

loader
I am the owner, or an agent authorized to act on behalf of the owner, of the copyrighted work described.
capcha
Download Presentation

PowerPoint Slideshow about 'Digital Testing: Scan Design' - benjamin


An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript
digital testing scan design

Digital Testing: Scan Design

Samiha Mourad

Santa Clara University

outline
Outline
  • Problems with sequential testing
  • What is scan
  • Types of scan
  • Types of storage devices
  • Scan Architectures
  • Cost of Scan
  • Partial Scan
  • Stitching flip-flops

Copyrights(c) 2001, Samiha Mourad

problems impeding testing
Problems Impeding Testing
  • Complexity testing sequential circuits due to
    • feedback loops
    • Placement of the circuit in a known state
    • high chance for hazard, essential hazard
  • Timing problems in general

Copyrights(c) 2001, Samiha Mourad

what is scan design
What is Scan Design
  • This DFT technique is used mainly for synchronous circuit represented by the Huffman model presented in Chapter 3
  • We assume the use of D-flip-flops only
  • A mux is placed at the input of each flip-flop in such a way that all flip-flops can be connected in a shift register for one mux selection and to work in normal mode in the other

Copyrights(c) 2001, Samiha Mourad

a generalized huffman model
A Generalized Huffman Model

Copyrights(c) 2001, Samiha Mourad

a generalized huffman model1
A Generalized Huffman Model

Copyrights(c) 2001, Samiha Mourad

what is scan design1
What is Scan Design
  • This DFT technique is used mainly for synchronous circuit represented by the Huffman model presented in Chapter 3
  • We assume the use of D-flip-flops only
  • A mux is placed at the input of each flip-flop in such a way that all flip-flops can be connected in a shift register for one mux selection and to work in normal mode in the other

Copyrights(c) 2001, Samiha Mourad

possible scan scheme
Possible Scan Scheme

Copyrights(c) 2001, Samiha Mourad

how scan dft works
How Scan DFT Works
  • The combinational part is partitioned:
    • Each input to the FF is considered an output to the circuit
    • each output of the FF is an input to the circuit
  • Connect the FF in a shift register and test them
  • Test the combinational part

Copyrights(c) 2001, Samiha Mourad

testing the combinational part
Testing the Combinational Part
  • Repeat until all patterns are applied.
      • a. Set SE = 1, shift in the initial values on the flip-flops. (These are the signals at the output of the latches for the first test pattern.)
    • b. SE = 0, apply a pattern at the primary inputs.
      • c. Clock the circuit once and observe the results at the primary outputs.
    • d. Clock the circuit M times.
  • End repeat.

Copyrights(c) 2001, Samiha Mourad

an example
An Example

Copyrights(c) 2001, Samiha Mourad

an example1
An Example

Copyrights(c) 2001, Samiha Mourad

inserting the muxes
Inserting the Muxes

Copyrights(c) 2001, Samiha Mourad

test application
Test Application

Copyrights(c) 2001, Samiha Mourad

types of storage devices
Types of Storage Devices
  • Multiplexed input flip-flop
  • Two-port flip-flop works with two nonoverlapping clocks
  • Latch-based Scan Design: requires
    • 2-latches clocked with non-overlapping clocks
    • 3-latch clocked with three phases

Copyrights(c) 2001, Samiha Mourad

2 port flip flops
2-Port Flip-flops
  • Port 1D works with CK1 in normal operation mode as well as at the capture mode of testing
  • Port 2D works with CK2 in shift mode
  • To avoid essential hazard during testing, CK1 and CK2 are non-overlapping phases. During t, non of them is working

Copyrights(c) 2001, Samiha Mourad

clocked transparent latches
Clocked Transparent Latches
  • (a) A D-latch implemented in NAND gates
  • (b) An extra NAND is added to suppress static hazard
  • (c) The corresponding Karnaugh map

Copyrights(c) 2001, Samiha Mourad

latches versus flip flops
Latches versus Flip-flops

Copyrights(c) 2001, Samiha Mourad

latch based shift mode
Latch-based Shift Mode
  • Because of the tranperancy property of the latches shown in the timing diagram of the previous slide
  • Latches cannot be used in a shift register unless every pairs works in a master-slave fashion as shown above
  • It is preferable that the two clocks be non-overlapping

Copyrights(c) 2001, Samiha Mourad

level sensitive latch
Level-sensitive Latch
  • The latch works with the 3 phases A, B and C
  • For normal operation, clocks B and C
  • For shift operation, clocks B and A
  • Two-port flip-flop works with two non-overlapping clocks

Copyrights(c) 2001, Samiha Mourad

polarity hold latch ibm
Polarity Hold Latch (IBM)

Copyrights(c) 2001, Samiha Mourad

scan design architectures
Scan Design Architectures
  • Several architectures:
    • Multiplexed flip-flops design
    • Level-sensitive scan design
    • Scan set scan design
  • Derivative of scan design:
    • Parallel scan chains
    • Partial scan

Copyrights(c) 2001, Samiha Mourad

level sensitive scan design
Level-Sensitive Scan Design
  • Each flip-flop of the original design is replaced by a polarity hold (an LSSD) latch
  • The configuration is shown in the next slide
  • The input of 2D in the first latch is scan-in
  • The output of the second latch of the last pair is scan-out
  • Of course here there is no scan control signal as in the muxed design studied earlier
  • Instead, the three phases A, B, and C operation control the normal and shift modes

Copyrights(c) 2001, Samiha Mourad

slide24
LSSD

Copyrights(c) 2001, Samiha Mourad

how does lssd work
How does LSSD Work?

1. Test the latches.

Set A = B = 1.

Apply 0 and 1 alternatively at SI.

Clock A, then clock B, N times.

2. Initialize.

Shift in the initial values on the flip-flops. (These are the signals at the output of the latches for the first test pattern)

Copyrights(c) 2001, Samiha Mourad

lssd testing
LSSD: Testing

Repeat until all patterns are applied.

a. Apply a pattern at the primary inputs.

b. Clock C; then clock B once and observe the results at the primary outputs.

c. Shift out the response

Apply the initialization for the next pattern at SI.

Clock A, then clock B, M times.

Observe at the primary outputs and the SO pins.

Copyrights(c) 2001, Samiha Mourad

scan set design
Scan Set Design
  • An architecture that allows on-line scan testing

Copyrights(c) 2001, Samiha Mourad

multiple scan chains
Multiple Scan Chains
  • Instead of stringing all the flip-flops or the latches in one shift register
  • Partition them is several chains
  • The advantages are:
    • compatible with multiple clock designs
    • Shorten test application time
    • Simplify the stitching of the flip-flops
  • But, may require extra pins

Copyrights(c) 2001, Samiha Mourad

multiple scan chains1
Multiple Scan Chains

Copyrights(c) 2001, Samiha Mourad

what why partial scan design
What & Why Partial Scan Design
  • To scan only a subset of the flip-flops
      • The circuit is easier to test by the sequential ATPG.
      • The area overhead is minimized.
      • The placement of the flip-flops is such that the interconnects are minimized.
      • The delays are shortened.

Copyrights(c) 2001, Samiha Mourad

partial scan design
Partial Scan Design
  • To scan only a subset of the flip-flops
  • How to select this subset?
  • It is an NP-complete problem
  • Heuristics on graph model to select the minimum vertex set (MVS) to transform the FSM into an acyclic graph

Copyrights(c) 2001, Samiha Mourad

an example2
An Example

Copyrights(c) 2001, Samiha Mourad

fault coverage
Fault Coverage
  • To scan only a subset of the flip-flops
  • How to select this subset?
  • It is an NP-complete problem
  • Heuristics on graph model to select the minimum vertex set (MVS) to transform the FSM into an acyclic graph

Copyrights(c) 2001, Samiha Mourad

partial scan
Partial Scan

Copyrights(c) 2001, Samiha Mourad

possible implementations
Possible Implementations

Copyrights(c) 2001, Samiha Mourad

scan chain order
Scan Chain Order

Copyrights(c) 2001, Samiha Mourad

the cost of scan design
The Cost of Scan Design
  • Area (muxes, extra routing)
  • Additional I/Os
  • Performance, delays within the flip-flops
  • Heat when testing at speed

Copyrights(c) 2001, Samiha Mourad

stitching effect
Stitching Effect

Copyrights(c) 2001, Samiha Mourad