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Due to the growing market of portable devices (such as

personal digital assistants, cellular phones, etc.), low power dissipation has become a very important issue in integrated circuit design. Among the many design techniques, the adiabatic approach is one method used in logic circuits to achieve low power design.

By applying the two ideas, one can achieve very low power dissipation in the circuit especially at low to moderate clock speed. The power saving of adiabatic circuit can reach up to more than 90 percent compared to conventional static CMOS circuit.

Adiabatic switching: dissipation in the circuit especially at low to moderate clock speed. The power saving of adiabatic circuit can reach up to more than

means that

the output node is charged slowly compared to its time

constant and we ensure that the voltage drop across the

transistor is relatively small at the time when the switching


On the other hand,

charge recycling:

means that

instead of dumping the charge to ground on every clock

cycle, the charge can be designed to flow back to the power


Adiabatic: occurring without loss or gain of heat dissipation in the circuit especially at low to moderate clock speed. The power saving of adiabatic circuit can reach up to more than

Conventional CMOS

Changing value of bit requires converting bit signal into heat

2 States: True, False

Speed is outstanding, but power dissipation is now a huge issue.

Adiabatic CMOS

Returns value (energy) of the bit back to the source

3 States: True, False, Off

Very low power dissipation is achieved at expense of speed.

CMOS transistors dissipate power when they switch. The main part of this

dissipation is due to the need to charge and discharge the gate capacitance C

through a component that has some resistivity R. The energy dissipated when

charging of the gate is

E =RC/T· CV 2

Where T is the time it takes the gate to charge or discharge.

Power Dissipation in Adiabatic Charging part of this





•=(2RC/T)(1/2 CV2)

Better than CMOS by a factor of (2RC/T) [2]“On resistance”Charging a load capacitance through a switch

In order part of this

to solve power disipation in switching , there are two fundamental rules

CMOS adiabatic

circuits must follow, the reasons for which are explained below.

The first is:

never to turn on a transistor when there is a voltage difference between the

drain and source.

The second says:

never to turn off a transistor that has current

flowing through it.

The second rule: part of this

that adiabatic circuits must follow is never to turn off a

transistor when there is current flowing through it.

The reason:

transistors are not perfect switches going from on to

off instantly. Instead, it gradually changes from on to off when the gate voltage

changes. Furthermore, the change is proportional to the speed atwhich the

gate voltage changes. A fact that when combined with the previous constraint,

implies that the transistor is in an “in between” state for a long period of time.

During this time, the voltage drop across the transistor greatly increases yet

the resistance is not high enough to bring power dissipation to zero.

Several designs of adiabatic CMOS circuits have been developed. Some of

themore interesting ones include Split-level Charge Recovery Logic (SCRL) .

SCRL (Splitlevel developed. Some ofCharge Recovery Logic)

ф developed. Some of









Heerl adiabatic circuit
HEERL developed. Some of Adiabatic circuit

Difficulties and Remedies for Adiabatic Circuits developed. Some of

Challenges of Recovery Circuits

1. Circuit implementation of time-varying power


2. Computations should be implemented by low overhead circuit

structures that use standard MOSFET devices

Problems of developed. Some ofAdiabatic Logic

There are two big challenges of energy recovering circuits:

It is very slow by today’s standards.

It requires 50% more area than conventional CMOS, and

simple circuit designs can be very complicated (consider

  • Fixing the Speed Problem… developed. Some of

  • Adiabatic circuits face difficulties in speed for a number

  • Of reasons:

    • •Charging time is inherently much slower than CMOS

    • •Increasing speed of adiabatic circuits enlarges power-clock data sensitivity

Final Remarks developed. Some of

Adiabatic circuitry will always be behind conventional CMOS in speed, but

as conventional CMOS gets faster Adiabatic circuitry will get faster as well.

It may become practical in the near future. Source Coupled Adiabatic

Logic is the most promising technology at this time.

Single phase clocking is less complicated to implement, but multiple phase

clocking is faster. Which will win?

If Source Coupled Adiabatic Logic prevails, great attention must go into

sinusoidal clock generator circuits.

Article Information developed. Some ofSemi-custom design of adiabatic adder circuitsKanchana Bhaaskaran, V.S.; Salivahanan, S.; Emmanuel, D.S.VLSI Design, 2006. Held jointly with 5th International Conference on Embedded Systems and Design., 19th International Conference onVolume , Issue , 3-7 Jan. 2006 Page(s): 4 pp. - Digital Object Identifier   10.1109/VLSID.2006.144

Summary: developed. Some of The paper presents the design, evaluation and performance comparison of cell based, low power adiabatic adder circuits operated by two-phase sinusoidal power clock signals, as against the literatures providing the operation of various adiabatic circuits, focusing on inverter circuits and logic gates, powered by ramp, three phase and four phase clock signals. The cells are designed for the quasi-adiabatic families, namely, 2N2P, 2N2N2P, PFAL, ADSL and IPGL for configuring complex adder circuits. A family of adiabatic cell based designs for carry lookahead adders and tree adders were designed. The simulations prove that the cell based design of tree adder circuits can save energy ranging from 2 to 100 over a frequency range of operation of 2MHz to 200MHz against the static CMOS circuit implementation. The schematic edit and T-Spice of Tanner tools formed the simulation environment.

Making Adiabatic Circuits Attractive for Todays VLSI developed. Some of

Industry by Multi-Mode Operation

- Adiabatic Mode Circuits -

Stephan Henzler, Thomas Nirschl, Matthias Eireiner,

Ettore Amirante, Doris Schmitt-Landsiedel

Institute for Technical Electronics

Technical University of Munich

Theresienstrasse 90

80290 Munich

[email protected]

Full adiabatic as well as quasi adiabatic circuit styles have been

proven to reduce the dynamic power dissipation of integrated

logic circuits considerably . Even leakage power is reduced

due to clocking of the power supply. However, adiabatic circuits

have not been widely accepted from industry as they are deemed

to allow no ultra high speed signal processing.

Most signal processing circuits have strongly changing speed have been

requirements. For example a mobile phone has high speed modes

like data transmission mode, telephone mode or imageprocessing

and video mode where maximum speed is required.

However, have been

there are also many modes where the system is snoozing or

waiting for interaction with the user, e.g. stand-by mode or PDAmode.

In these modes low power dissipation is the main challenge.

Speed is of minor interest, as it is not needed or limited

by other constraints like the handling of the user.

Hence a first

step to integrate adiabatic circuit styles into such applications

would require a circuit style that is capable of adiabatic lowpower operation but also of non adiabatic high-speed operation.

Any Question have been