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Status of the electronics systems of the MEG experiment. HV. 1:1. 1:1. Active Splitter. Active Splitter. 1:1. 1:1. Trigger. 216. 4:1. 4:1. Trigger. front. PMT. atten. Trigger. LXe. 630. lateral. PMT. 3 crates. HV. DRS. DRS. 1:1. Active Splitter. 60. 120. DRS. bars.

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electronic chain

HV

1:1

1:1

Active

Splitter

Active

Splitter

1:1

1:1

Trigger

216

4:1

4:1

Trigger

front

PMT

atten

Trigger

LXe

630

lateral

PMT

3 crates

HV

DRS

DRS

1:1

Active

Splitter

60

120

DRS

bars

PMT

Ramp

1:1

DRS

4:1

TC

DRS

HV

DRS

8:1

APD

Pre-Amp

fibers

512

5 crates

HV

Hit

registers

32

Wires

Pre-Amp

576

DC

1156

4 boards

Strips

Pre-Amp

Aux. devices

Electronic chain
daq and control

pE5 area

‘counting room’

Trigger

Trigger

Trigger

Trigger

clock

start

stop

sync

Front-End PCs

Main DAQ PC

PC (Linux)

PC (Linux)

PC (Linux)

PC (Linux)

Run start

Run stop

Trigger config

PC (Linux)

DRS

PC (Linux)

DRS

Busy

Error

PC (Linux)

DRS

DRS

PC (Linux)

DRS

PC (Linux)

DRS

20 MHz

clock

PC (Linux)

Hit

registers

Event

builder

PC (Linux)

PC (Linux)

Gigabit

Ethernet

Trigger signal

Event number

Trigger type

PC (Linux)

PC (Linux)

On-line farm

storage

DAQ and control

Ancillary

system

3 crates

6 crates

slide5
HV

Active down regulation of an external HV supply

PSI design

  • 10 chn per board
  • 180 chn per 3 HE crate
  • Back side connector
  • Total of 6 crates

4 different requirements:

  • Lxe: 1000V , 100 uA
  • TC bars: 2400V, 1 mA
  • TC curved: 500V, <1 uA
  • DC: 2400V, ~1 uA

Commercial HV suppliesdelivered

Mass productionin progress

Installation inSeptember

splitter layout
Splitter layout
  • ERNI high bandwidth output connector
  • crosstalk with ERNI connector plus 2m cable is ~ 0.6%

Trigger or DRS

Input

DRS

Trigger

Power

backplane layout
Backplane layout
  • Test circuit was implemented on backplane
  • Debug completed
  • PCB production in progress, mounting in house
crates
Crates
  • Mechanic parts and fans delivered
  • Power supplies delivered and tested

Frontal panel

Back panel

Output (5V-36A)

cables
Cables

Inputs

  • Single coaxial cable (RG178 – 9m long) bundled into a polyester braided sleeve
  • Negligible crosstalk between cables.

DRS outputs

  • High bandwidth output (DRS)
  • high density twisted pairs cable (0.68 pitch) 2 m long with one flat zone in the middle (Amphenol SPECTRASTRIP 68p)

Trigger outputs

  • Low density twisted pairs cable (1.27 pitch) 2 m long with 2 flat zone (3M 34p/10p)
splitter summary
Splitter Summary

Splitter

  • first prototype finished in may successfully
  • PCB production started the first of June
  • PCBproduction time one month
  • Component procurement in progress
  • Board mounting2 weeks end of July
  • Board test1 week
  • Boards ready by the beginning of September

Backplane

  • Crates and power supplydelivered
  • backplane production in Lecce

Cables

  • Trigger cables ready
  • LXe cables in production
  • DRS cables in production

Installation

  • Foreseen between September 5 and 20
pmt ramp generator
PMT ramp generator

B

to Splitter

Analog signals

to DRS and trigger

PMT

B

S

TC Analog Sign. Monitor

Passive

Splitter

RAMP

GEN.

D/D

6U Eurocards boards

8 boards

to Splitters

Signals to DRS

Dual Threshold OR

Constant Fraction OR

Leading edge discriminator

NIM Signal

for any possible use

production
Production

PMT ramp generator

  • Design of the final boards in progress
  • Mass production September (?)
  • system delivery 8 boards October (?)

APD pre amplifiers

  • First prototype with problems on IC and cross talk
  • Second prototype design and test completed
  • Mass production and test in progress
  • system delivery end of July

APD hit registers

  • board design completed
  • Production and test in progress
  • system delivery (6 boards – 6U VME) end of July
trigger boards

Type2

Front end

Ancill

Type1

TriggerBoards
system test
System test

4 Type1

2 Type2

2 Ancillary

  • Synchronous operation
  • No transmission errors
splitter type1 connection
Splitter-Type1 connection

Alpha and cosmic muon events from the Pisa facility

number of boards status
Number of boards: status

Done !

Done !

Boards Type2

  • 10 funded
  • 5 needed
  • 10 delivered
  • 10 tested

Boards Type1

  • 48 funded
  • 36 needed
  • 40 delivered
  • 8 not completely mounted
  • 40 tested

Front-End Boards

  • 800 funded
  • 576 needed
  • 800 delivered
  • 320 tested

Boards Ancill

  • 8 funded
  • 4 needed
  • 4 delivered
  • 4 not completely mounted
  • 2 tested
firmware v1 0 present status
Firmware V1.0 Present Status

Type1 : VIRTEX II- PRO (XC2VP20-7-FF1152)

  • Type1-0 LXe front face
  • Type1-1 LXe lateral faces 
  • Type1-2 LXe top,bottom and back face 
  • Type1-3 TC bars 
  • Type1-4 TC fibers 
  • Type1-5 DC 
  • Type1-6 Auxiliary devices 
  • Type1-7 LXe back face x

Type2 : VIRTEX II- PRO (XC2VP40-7-FF1152)

  • Type2-0 Final Level completed  
  • Type2-1 LXe front+up/down faces 
  • Type2-2 LXe lateral faces 
  • Type2-3 TC
board type31
Board Type3

Modified Type1 boards to produce an auxiliary digitization of the LXe signals

  • Type3 board 32 channels
  • Number of boards for the LXe lateral sides(612 chn): 20
  • Boards design : ~ready
  • PCB prototype : end of July
  • Component delivery:(12 weeks)~ beginning of September
  • Test: September
  • Production: October
  • Installation: end of October
comments on trigger
Comments on trigger

Installation

  • Ready: any time from beginning of Jul. to end of Aug.
  • Should follow the NaI moving system
  • Should precede the electronic integration Sep.
  • DAQ computers

Configuration

  • Baseline version V1.0 written
  • Needs tuning, at least 1 month during purification
  • Needs analysis tools, under development

Documentation

  • Hardware register list available
  • Almost available for Type1
  • In progress for Type2
slide26
DRS
  • DRS2 available for all channels
  • New PMC card finished
    • Reduced noise 1.2 mV → 0.5 mV RMS
    • Self-calibration on card
    • Mass production started
    • cards expected in August
  • PSI GPVME boards in production
    • Delivery end of August
drs2 issues
DRS2 issues

All issues could be resolved as planned

slide28
DRS3
  • DRS3 design finished
  • Prototypes expected in August
  • Tests foreseen at the end of the year
drs3 layout
DRS3 layout
  • Smaller “standard cells”
  • Totally > 600,000 transistors
  • Smaller package (QFP64)
  • 12 channels/chip
  • ROI readout and parallel readout to reduced dead time:230 ms → 50 ms → 5 ms
drs and trigger crates
DRS and Trigger Crates

20 cm

Issue: “Splitter” rack cannot be accessed easily from back side!

Power distribution box

daq cluster layout
DAQ Cluster Layout

/home/meg

|-- root <- ROOTSYS

|-- midas <- MIDASSYS

|-- mxml

|-- rome <- ROMESYS

`-- meg <- MEGSYS

|-- meganalyzer

|-- megbartender

|-- megmc

`-- online

|-- drivers

|-- eventbuilder

|-- frontend

|-- slowcontrol

| |-- bts

| |-- calorimeter

| `-- scfe

|-- trigger

`-- VPC

80 GB System Disk

RAID 1 (Mirror)

VME-Interface

Front-End #1

80 GB System Disk

RAID 1 (Mirror)

VME-Interface

Front-End #2

. . .

NFS

80 GB System Disk

RAID 1 (Mirror)

SC-FE

1.2 TG Data Disk

RAID 5

/home/meg

Data rate

100 MB/s

Back-End

front end computers
Front-end computers
  • Two DAQ computer installed with DAQ software
  • Remaining computers delivered
  • Installation end of July

GBit Switch

Front-end #1

Back-end1.2 TB disk

offline cluster
Offline Cluster

15 x 500 GB SATA

Sun Fire x4100 quad core 4 GB

Sun Fire x4100 quad core 4 GB

Fiber Channel Switch

Sun Fire x4100 quad core 4 GB

GBit Ethernet

Sun Fire x4100 quad core 4 GB

Sun Fire x4100 quad core 4 GB

  • Ordered on June 14th: 20 cores + 30 TB disk
  • Easily extensible
  • Redundancy through GFS/GPFS file systems
  • GBit link to online cluster requested
scs 2000
SCS-2000
  • Replaces SCS-1001 unit
  • 64 I/O lines (analog, digital, opto-coupler, PT100, etc.)
  • Outputs stable during CPU firmware upgrade (→ BTS control)
  • “Soft” fuse
  • LED pulser (40 lines, computer controllable)
bts slowcontrol
BTS slowcontrol
  • Slowcontrol back-end to MSCB slow control units
  • Integrated in MIDAS history system
  • Monitoring and control though MIDAS web pages
  • More pages added as SC equipment gets operational
conclusions
Conclusions
  • All the key elements of the electronic system are available for integration in September
  • Some parts will arrive with ~1 month delay