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Status of the electronics systems of the MEG experiment

Status of the electronics systems of the MEG experiment. HV system. External HV power supply Control and regulation through MSCB 10 chn per board 180 chn per 3 HE crate Back side connector. 4 different requirements: Lxe: 1000V , 100 uA TC bars: 2400V, 1 mA TC curved: 500V, <1 uA

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Status of the electronics systems of the MEG experiment

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  1. Status of the electronics systems of the MEG experiment

  2. HV system • External HV power supply • Control and regulation through MSCB • 10 chn per board • 180 chn per 3 HE crate • Back side connector 4 different requirements: • Lxe: 1000V , 100 uA • TC bars: 2400V, 1 mA • TC curved: 500V, <1 uA • DC: 2400V, ~1 uA 50 channels successfully tested on the LP for a couple of months 1000 channels for LXe, TC and DC in production Ready by June ‘06

  3. Splitter boards • Studies on the cross-talk on twisted cables suggested better insulation among the full-bandwidth output for DRS • High bandwidth output layout was changed for new connector from JAE • Cross-talk expected ~< 1% trigger/DRS Input DRS trigger Power

  4. Splitter backplane layout The DRS calibration circuit has been included on the backplane It provides programmable DC levels on all the splitter outputs (0.-2. V at 1mV resolution) Control through MSCB A special calibration signal is provided by the trigger system Example of a calibration pattern

  5. Splitter orders status • Parts all ordered, many arrived: • Cables • Input cables + carriers: partially delivered • Output 34p tw 2.54 pitch cables + connectors (trigger): delivered • Output 10p tw 2.54 pitch cables + connectors (sum) : delivered • Output 68p tw 1.27 pitch cables + connectors (DRS) : ordered • Crates • 9U Crates with accessories: ordered • Fans: delivered • Power supply: ordered • Backplane printed circuit: ordered • Backplane connectors: delivered • Cards • Printed circuit: ordered • Card components: ordered • Front panels: ordered • Mechanical accessories: delivered • Installation expected in May ‘06

  6. TC discriminator cards Timing measurement • Eurocard 6U height • 8 boards • Hosted in the splitter crate B to Splitter Analog signals to DRS and trigger B PMT S TC Analog Sign. Monitor Passive Splitter Prototype under test at Frascati Delivery in May Installation in June RAMP GEN. D/D to Splitters Signals to DRS Dual Threshold Discriminator NIM Signal for any possible use

  7. 8 Ch APD F.E. Card Concentrator Card TC fibers TC mezzanine board Output for the trigger system APD F.E. card: • Front-end prototype for APD under test • Final prototypes construction will start by 15th of february • Final production: 3 weeks after acceptance. • Delivery expected in May • Same schedule for concentrator cards and mezzanine for VME-VPC board. • FPGA CODE (V1.01) ready. Soon will start the evaluation process that will take 1 months PSI GPVME board

  8. 14 boards . . . Type2 Type2 Type2 Type2 Type2 14x 48 Type1 Type1 Type1 Type1 Type1 Type1 Type1 Type1 Type1 Type1 Type1 Type1 4 4 4 4 4 16 16 16 16 16 16 9 boards . . . 9x 48 2 boards LXe front face (216 PMTs) 2 x 48 Trigger system structure 5+5+2 boards LXe lateral faces back (216 PMTs) 4 in 1 lat. (144x2 PMTs) 4 in 1 up/down (54x2 PMTs) 4 in 1 . . . 1 board 9 x 48 2 x 48 1 board Timing counters curved (640 APDs) 8 in 1 u/d stream (30x2 PMTs) 1 x 48 1 board 2 boards Drift chambers 16+16 channels 2x 48 Auxiliary devices 16 channels 1 x 48

  9. Type1 Type2

  10. Short summary • Test of the board Type1 completed • Test of the board Type2 completed • System test completed • Corrections and improvements • One missing connection per board • Control of the power up procedure • Increased the read-out speed (~50 events/s) • Final PCB productionin progressdelivery confirmed for Feb. 10th ’06 • Board mountingassignedcompany waiting for PCB • Crates 6U (PSI), crate 9U (CAEN), interfaces ordered • On-line PC (DAQ model) waiting • Two test station are ready • Firmware designin progressstrongly dependent on PMT cabling • Installation at PSI, together with the DAQ june ’06

  11. Auxiliary digitization We consider useful exploiting the trigger FADC as auxiliary digitazing system 100MHz, 10 bits, 5 s depth, no fanin Two options are considered Modified Type1 boards from16to32channels Requires manpower… Use of the Type1 boards as they are, without mounting part of the components Requires 2 crates… both solutions have the same cost

  12. DRS2 - new CMC card • Better analog design (lower crosstalk and noise • Moved chips more to front • Dedicated clock input • Dual FADC • Temperature sensor • 1k EEPROM 128 DRS2 channels ready Noise level with the new CMC

  13. DRS2 - Clock “nonlinearity” 30ns ns bin

  14. R ~1mA Vin Vout read write . . . C I = c1 * Vin + c2 * Vin * kT DRS2 – cell self-heating “Differential Pair” Vin Vout write C Ib/2 Ib/2 Ib • Current depends on “history” of cell • Quadratic effect • Small below input voltage of 0.5V • Solution: OTA readout + -

  15. DRS2 - ghost pulses signal after one turn after two turns 2% >0.5%

  16. DRS2 vs DRS3

  17. DRS short summary • DRS2 available for all experiment channels: LXe, TC and DC • DRS2 installation foreseen in june 2006 • Design of theDRS3 started (with the help of a new engineering ) • Solutions for the DRS2 problems were identified • Replacement of part or all DRS2 with DRS3 expected during 2007 beam shutdown

  18. DAQ Readout speed • Struck SIS3100 • VPC board with CMC • 2eVME transfer protocol • Desktop PC (2.6 GHz P4) T = 125us + size/84 MB/sec 25 ms/event at full readout DAQ computers Producer: www.thomas-krenn.com Cost: 1800 € • Hot–plug cooler • Redundant power supply • Hot swap hard disks • Remote management card

  19. Slow Control System - 2000 Based on Midas Slow Control Bus Evolution of the SCS 1000 Slow control of all MEG equipments • 8 banks @ 8 In- or Outputs → 64 I/O • Each bank may contain • Output: 5V, 24V, 4-20mA, ±10V, LED pulser • Input: 5V, 24V, 4-20mA, ±10V, comparator • Outputs stable during CPU software upgrade and reboot • CPLD can be used for hard-wired logic → control operation w/o CPU

  20. Conclusions of the last BVR • An electronics integration scheme has been developed • Minor details needs to be fixed – done! • All key electronics elements will be available before March 06 moved to June 06 • A test of the final electronics systems, together with crates, in magnetic field environment is planned in autumn done!

  21. HV 1:1 1:1 Active Splitter Active Splitter 1:1 1:1 Trigger 216 4:1 4:1 Trigger front PMT atten Trigger LXe 612 lateral PMT 3 crates HV DRS DRS 1:1 Active Splitter 60 120 DRS bars PMT Ramp 1:1 DRS 4:1 TC DRS HV DRS 8:1 APD Pre-Amp fibers 640 6 crates HV Hit registers 32 Wires Pre-Amp 576 DC 1156 4 boards Strips Pre-Amp Aux. devices Electronic chain

  22. pE5 area ‘counting room’ Trigger Trigger Trigger Trigger clock start stop sync Front-End PCs Main DAQ PC PC (Linux) PC (Linux) PC (Linux) PC (Linux) Run start Run stop Trigger config PC (Linux) DRS PC (Linux) DRS Busy Error PC (Linux) DRS DRS PC (Linux) DRS PC (Linux) DRS 20 MHz clock PC (Linux) Hit registers Event builder PC (Linux) PC (Linux) Gigabit Ethernet Trigger signal Event number Trigger type PC (Linux) PC (Linux) On-line farm storage DAQ and control Ancillary system 3 crates 6 crates

  23. Rack space

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