-2. 10. noise + interference. Base-station. -3. 10. Direct. Reflections. -4. 10. Execution time (in seconds). User 1. User 2. -5. 10. Single DSP implementation. 2 DSP implementation. Target data rate - 128 Kbps/user. 2 DSPs + 2 FPGAs. -6. 10. 0. 5. 10. 15. 20. 25. 30.
Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.
noise + interference
Execution time (in seconds)
Single DSP implementation
2 DSP implementation
Target data rate - 128 Kbps/user
2 DSPs + 2 FPGAs
Come from a
- or a -
BER vs Path loss in dB
Then, take these algorithms (theory)…
…to implementation in a prototype
Scheme with RF
DSP + FPGA
Performs channel estimation
2.4 GHz ISM hardware
DSP + FPGA
DSP + FPGA
Path loss in dB
Performs RF reception
Next Generation Cellular System
Guaranteed Quality of service
Higher Data Rates: 2 Mbps, 384 Kbps, 128 Kbps.
RENE: Wireless Cellular RadioSrikrishna Bhashyam, Sridhar Rajagopal, Kanu Chadha, Dinesh Rajan, Bryan Jones, Yuanbin Guo, Ahmad Khoshnevis, Frank Livingston, Charles Camp, Behnaam Aazhang, Joseph Cavallaro
Sent via RF (radio
waves) over the air
RF receiver / demodulator
Multiprocessor Basestation Implementation
The Wireless Channel
The Sundance board contains 2 DSPs and 2 FPGAs.
The channel estimator and detector have been implemented on this platform. Measurements show a 2 DSP solution to be faster than a single DSP solution. Projects demonstrate using both DSPs and FPGAs provides even greater performance.
Larger values are worse (slower)
Modeling of RF in W-CDMA with SystemView
N: 2~64 --wideband
Complete system evaluation on multiple DSPs and RF hardware
Carrier offset and synchronization - multiple users
Mobile handset - low power, fixed point DSP implementation
Integrating physical layer with higher layers
Task partitioning and Parallel architectures for acceleration