ECE 342 Review - 1

1. ECE 342 Review - 1 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu

2. Thevenin Equivalent • Principle • Any linear two-terminal network consisting of current or voltage sources and impedances can be replaced by an equivalent circuit containing a single voltage source in series with a single impedance. • Application • To find the Thevenin equivalent voltage at a pair of terminals, the load is first removed leaving an open circuit. The open circuit voltage across this terminal pair is the Thevenin equivalent voltage. • The equivalent resistance is found by replacing each independent voltage source with a short circuit (zeroing the voltage source), replacing each independent current source with an open circuit (zeroing the current source) and calculating the resistance between the terminals of interest. Dependent sources are not replaced and can have an effect on the value of the equivalent resistance.

3. Thevenin Equivalent - Example Circuit for calculating impedance Calculating Thevenin voltage KCL law at node A’ gives 1+Iy = Ix Also KVL gives 10=2Iy+3Ix Combining these equations gives Ix = 2.4 mA From which we calculate Vx = Vth=3(2.4)=7.2 V

4. PN Junction • When a p material is connected to an n-type material, a junction is formed • Holes from p-type diffuse to n-type region • Electrons from n-type diffuse to p-type region • Through these diffusion processes, recombination takes place • Some holes disappear from p-type • Some electrons disappear from n-type A depletion region consisting of bound charges is thus formed Charges on both sides cause electric field  potential = Vo

5. Diode Characteristics • Three distinct regions • The forward-bias region, determined by v > 0 • The reverse-bias region, determined by v < 0 • The breakdown region, determined by v < -VZK

6. Diode I-V Relationship • Breakdown • Electric field strong enough in depletion layer to break covalent bonds and generate electron-hole pairs. Electrons are then swept by E-field into the n-side. Large number of carriers for a small increase in junction voltage

7. The Diode • Diode Properties • Two-terminal device that conducts current freely in one direction but blocks current flow in the opposite direction. • The two electrodes are the anode which must be connected to a positive voltage with respect to the other terminal, the cathode in order for current to flow.

8. Ideal Diode Characteristics I > 0 V < 0 OFF ON

9. Ideal Diode Characteristics

10. Diode Models Piecewise Linear Constant-Voltage-Drop Exponential

11. Diode Models Small-signal Ideal-diode

12. Piecewise-Linear Model

13. Diode Circuit Example 1 IDEAL Diodes Assume both diodes are on; then At node B D1 is conducting as originally assumed

14. Diode Circuit Example 2 Assume both diodes are on; then IDEAL Diodes At node B original assumption is not correct … assume D1 is off and D2 is on D1 is reverse biased as assumed

15. Example Two diodes are connected in series as shown in the figure with Is1=10-16 A and Is2 =10-14A. If the applied voltage is 1 V, calculate the currents ID1 and ID2 and the voltage across each diodeVD1 and VD2. The diode equations can be written as: from which and from which Using KVL, we get

16. Small Signal Model Approximation - valid for small fluctuations about bias point Total DC applied (small)

17. Voltage Regulator - Example Assume n=2 and calculate % change caused by a ±10% change in power-supply voltage (a) with no load (b) with 1-kW load • Nominal value of current is: • Incremental resistance for each diode: • Resistance for all 3 diodes: • Voltage change

18. Voltage Regulator – Example (con’t) • When 1kW load is connected, it draws a current of 2.1 mA resulting in a decrease in voltage across the 3 diodes given by

19. Diode as Rectifier While applied source alternates in polarity and has zero average value, output voltage is unidirectional and has a finite average value or a dc component

20. Diode as Rectifier vs is a sinusoid with 24-V peak amplitude. The diode conducts when vs exceeds 12 V. The conduction angle is 2q where qis given by The conduction angle is 120o, or one-third of a cycle. The peak value of the diode current is given by The maximum reverse voltage across the diode occurs when vs is at its negative peak: 24+12=36 V

21. Diode Circuits - Rectification C must be large enough so that RC time constant is much larger than period Rectification with ripple reduction.

22. NMOS Transistor • NMOS Transistor • N-Channel MOSFET • Built on p-type substrate • MOS devices are smaller than BJTs • MOS devices consume less power than BJTs

23. MOS Regions of Operation Resistive Triode Nonlinear Saturation Active

24. MOS – Triode Region - 1 Cox: gate oxide capacitance m: electron mobility L: channel length W: channel width VT: threshold voltage

25. MOS – Triode Region - 2 • Charge distribution is nonuniform across channel • Less charge induced in proximity of drain

26. MOS – Active Region Saturation occurs at pinch off when (saturation)

27. NMOS – IV Characteristics characteristics for a device with k’n(W/L) = 1.0 mA/V2.

28. Example • An MOS process technology has Lmin= 0.4 mm, tox= 8 nm,m = 450 cm2/V.s, VT = 0.7V • Find Cox and kn’= mnCox • W/L= 8 mm/0.8mm. Calculate VGS, VDSminfor operation in saturation with ID= 100 mA • Find VGS for the device in (b) to operate as a 1 kW resistor for smallvDS

29. Example - Solution For operation in saturation region

30. Example – (con’t) Triode region with vDS very small

31. Body Effect • The body effect • VTvaries with bias between source and body • Leads to modulation of VT Potential on substrate affects threshold voltage Fermi potential of material Body bias coefficient

32. Channel-Length Modulation With depletion layer widening, the channel length is in effect reduced from L to L-DL Channel-length modulation This leads to the following I-V relationship Where l is a process technology parameter

33. Channel-Length Modulation Channel-length modulation causes iD to increase with vDS in saturation region

34. Problem A MOSFET has VT= 1 V with measured data: VGS(V) VDS(V) ID(mA) 2 1 80 2 8 91 Findl

35. Problem (cont’) Find iD at pinchoffVDSP = VGS-VT =1V

36. Problem (cont’)

37. MOSFET Circuit at DC – Problem 1 The MOSFET in the circuit shown has Vt = 1V, kn’= 100mA/V2 and l = 0. Find the required values of W/L and of R so that when vI=VDD=+5 V, rDS=50 W and vo= 50 mV.

38. MOSFET Circuit at DC – Problem 1 (cont’)

39. MOSFET Circuit at DC – Problem 2 The NMOS transistors in the circuit shown have Vt = 1V, mnCox = 120mA/V2, l = 0 and L1=L2=1mm. Find the required values of gate width for each of Q1 and Q2 and the value of R, to obtain the voltage and current values indicated.

40. PMOS Transistor • All polarities are reversed from nMOS • vGS, vDSand Vtare negative • Current iDenters source and leaves through drain • Hole mobility is lower  low transconductance • nMOS favored over pMOS

41. Complementary MOS • CMOS Characteristics • Combine nMOS and pMOS transistors • pMOS size is larger for electrical symmetry

42. CMOS • Advantages • Virtually, no DC power consumed • No DC path between power and ground • Excellent noise margins (VOL=0, VOH=VDD) • Inverter has sharp transfer curve • Drawbacks • Requires more transistors • Process is more complicated • pMOS size larger to achieve electrical symmetry • Latch up

43. CMOS Switch – Off State • OFF State (Vin: low) • nMOS transistor is off • Path from Vout to V1 is through PMOS Vout: high

44. CMOS Switch – On State • ON State (Vin: high) • pMOS transistor is off • Path from Vout to ground is through nMOSVout: low

45. CMOS Inverter • Short switching • transient current •  low power

46. Voltage Transfer Characteristics (VTC) The static operation of a logic circuit is determined by its VTC • In low state: noise margin is NML • In high state: noise margin is NMH NML NMH VIL and VIH are the points where the slope of the VTC=-1 • An ideal VTC will maximize noise margins Optimum:

47. Switching Time & Propagation Delay input output

48. CMOS Switch CMOS switch is called an inverter The body of each device is connected to its source  NO BODY EFFECT

49. CMOS Switch – Input Low NMOS rdsn high PMOS rdsp islow

50. CMOS Switch – Input High NMOS rdsn is low PMOS rdsp high