bist for logic and memory resources in virtex 4 fpgas l.
Download
Skip this Video
Loading SlideShow in 5 Seconds..
BIST for Logic and Memory Resources in Virtex-4 FPGAs PowerPoint Presentation
Download Presentation
BIST for Logic and Memory Resources in Virtex-4 FPGAs

Loading in 2 Seconds...

play fullscreen
1 / 16

BIST for Logic and Memory Resources in Virtex-4 FPGAs - PowerPoint PPT Presentation


  • 480 Views
  • Uploaded on

BIST for Logic and Memory Resources in Virtex-4 FPGAs Sachin Dhingra, Daniel Milton, and Charles Stroud Electrical and Computer Engineering Auburn University Outline of Presentation Overview of Virtex-4 Architecture Operational Features Built-In Self-Test Architecture BIST for PLBs

loader
I am the owner, or an agent authorized to act on behalf of the owner, of the copyrighted work described.
capcha
Download Presentation

PowerPoint Slideshow about 'BIST for Logic and Memory Resources in Virtex-4 FPGAs' - arleen


An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript
bist for logic and memory resources in virtex 4 fpgas

BIST for Logic and Memory Resources in Virtex-4 FPGAs

Sachin Dhingra, Daniel Milton, and Charles Stroud

Electrical and Computer Engineering

Auburn University

outline of presentation
Outline of Presentation
  • Overview of Virtex-4
    • Architecture
    • Operational Features
  • Built-In Self-Test
    • Architecture
    • BIST for PLBs
    • BIST for LUT-RAMs
    • BIST for Block RAMs
  • Experimental Results
    • Test Time
    • Memory Storage Requirements
  • Summary

North Atlantic Test Workshop

xilinx virtex 4 fpgas

PC

PC

Xilinx Virtex-4 FPGAs
  • Configuration memory: 4.7M to 50.8M bits of RAM
  • PLBs: 1,536 to 22,272
    • 4 LUTs/RAMs (4-input)
    • 4 LUTs (4-input)
    • 8 FF/latches
  • Block RAMs: 48 to 552 18K-bit dual-port RAMs
    • Also operate as FIFOs
  • DSP cores: 32 to 512, each includes:
    • 18x18-bit multiplier
    • 48-bit adder & accumulator
  • PowerPC processors: 0 to 2
    • Supports soft processor cores
    • Can write & read configuration memory

North Atlantic Test Workshop

bist for fpgas
BIST for FPGAs
  • Basic idea: reprogram FPGA to test itself
    • No area overhead or performance penalties
  • Applicable to all levels of testing
    • Application independent testing
      • A generic test approach for a generic component
    • Good diagnostic resolution
  • Cost:
    • Memory to store BIST configurations
      • Goal: minimize number of configurations
    • Download time to execute BIST configurations
      • Goal: minimize downloads and/or download time

North Atlantic Test Workshop

bist for plbs

TPG

TPG

Row of TPGs

Row ofBUTs

Global routing

Row ofORAs

Row ofBUTs

BUT

BUT

Row ofORAs

Local

routing

Row ofBUTs

ORA

ORA

Row ofORAs

BUT

BUT

Local

routing

Row ofBUTs

BUT

BUT

BUTs

Global routing

ORA

ORA

ORAs

BUTs

ORAs

BUTs

BUT

BUT

ORAs

BUTs

TPGs

BIST for PLBs
  • Program PLBs as
    • Test Pattern Generators (TPGs)
    • Output Response Analyzers (ORAs)
    • Logic blocks under test (BUTs)
  • Two test sessions
    • Row or column orientation
    • Good for dynamic partial reconfiguration

North Atlantic Test Workshop

virtex 4 logic bist

=TPG

=BUT

=ORA

Test Session

Virtex-4 Logic BIST
  • TPGs constructed from DSPs
    • Accumulates constant 0x691
      • Produces pseudo-exhaustive patterns
    • Two TPGs per 4 rows of CLBs
    • Each TPG drives alternating columns of BUTs
  • ORAs in alternate columns
    • 2 test sessions needed
  • BUTs
    • Logic slices need 10 configs
    • Memory slices need 12 configs
      • Not counting LUT RAMs
      • Includes 2 for testing Shift Registers
    • All slices test concurrently

North Atlantic Test Workshop

virtex 4 lut ram bist

TPG 2

TPG 1

ORA

SLICEL

ORA

SLICEL

DSP

counter

DSP

counter

ORA

SLICEL

ORA

SLICEL

address

block RAM

data out

address

block RAM

data out

BUT

SLICEM

BUT

SLICEM

BUT

SLICEM

BUT

SLICEM

Virtex-4 LUT RAM BIST
  • TPGs constructed from
    • DSPs used as counter
    • Block RAM used as ROM
      • Store March Y test patterns
      • March DPR for dual-port
  • Memory slice LUT RAMs
    • 64x1 single-port
    • 32x2 single-port
    • 16x2 dual-port
  • ORAs in logic slices
    • Only 1 test session
  • BIST structure
    • Groups of 4 rows
    • 2 TPGs per 4 rows
      • Drive memory slices in those rows

North Atlantic Test Workshop

bist for block rams dsps

=Core Under Test

=ORA PLBs

=TPG PLBs

=unused PLBs

BIST for Block RAMs & DSPs
  • Circular Comparison ORA
    • Implemented in PLBs
    • 1 ORA/core output
      • Maximizes diagnostic resolution
  • Two TPGs
    • Implemented in PLBs
    • Algorithms are a function of the BUT

North Atlantic Test Workshop

march lr test for rams
March LR Test for RAMs
  • Detects
    • neighborhood pattern sensitivity faults
    • intra-word coupling faults
    • bridging faults
  • Notation
    • ↓ = address downward
    • ↑ = address upward
    • ↨ = address either way
    • w0 = write 0
    • r1 = read 1
  • Length of test = 16N
    • N = number of address locations
  • Word-oriented memory Background Data Sequences (BDS) to detect pattern sensitivity & coupling faults
    • # BDS = log2(K)+1, where K = data width
    • Length of test = (16+7log2(K))N

North Atlantic Test Workshop

virtex ii block ram bist
Virtex II Block RAM BIST

N = # of block RAMs

D = # of data bits

Total clock cycles = 829,952

Includes testing programmable controls:

Active level of reset, clock enable, write enable

Active edge of clock

Includes testing programmable write modes:

Write-first, Read-first, No-change

North Atlantic Test Workshop

virtex 4 block ram bist
Virtex-4 Block RAM BIST

Configurations 1-5 in one BIST download

Configurations 6-10 in another download

Generic TPG for each download

North Atlantic Test Workshop

virtex 4 block ram bist12
Virtex-4 Block RAM BIST
  • FIFOs
    • Test full and empty flags
    • Test “almost” flags (full and empty) via dynamic partial reconfiguration during BIST configuration
      • Significant reduction in number of downloads
  • ECC RAM
    • Problem: detecting faults in FT circuit
    • Solution: initialize RAM with Hamming errors
      • Detect faults in bit error detection/correction circuit & status outputs during full read cycle of RAM BIST
      • Detect faults in Hamming code generation circuit during full write then read cycle of RAM BIST

North Atlantic Test Workshop

reducing test time
Reducing Test Time
  • Orient BIST architecture to configuration memory
    • Keep routing constant between configurations
  • Downloading BIST configurations
    • Partial reconfiguration
      • Frame Data Register
        • Allows multiple frame writes with same data
      • Reduces # frames written for configurations
        • Optimize ordering of BIST configurations
  • Retrieving BIST results
    • Partial configuration memory readback
    • Dynamic partial reconfiguration
      • Read BIST results after set of BIST configurations
        • Slight loss of diagnostic resolution

North Atlantic Test Workshop

reducing test time14

Virtex

End Partial

Mem RB

Virtex

Virtex

Virtex

Reducing Test Time

Partial

Mem RB

Partial

Reconfig

Full

Mem RB

Full

Config

Download

Technique

ORA

Results

Retrieval

Technique

North Atlantic Test Workshop

reducing test time cont d

End Partial

Mem RB

Reducing Test Time cont’d

Partial

Mem RB

Partial

Reconfig

Full

Mem RB

Full

Config

Download

Technique

ORA

Results

Retrieval

Technique

North Atlantic Test Workshop

summary
Summary
  • Virtex-4’s large size and specialized cores pose challenges for developing efficient tests
    • BIST Techniques
      • Partial Reconfiguration
      • Regular Test Structures
  • New architectural operational features of Virtex-4 improve the efficiency of BIST
    • BIST Results
      • Test time improvements
        • Over 12X improvement in Virtex-4 compared to 5X for Virtex
      • Memory storage reduction
        • 5X improvement for Virtex-4, 3X for Virtex

North Atlantic Test Workshop