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Spectral BIST

Spectral BIST

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Spectral BIST

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  1. Spectral BIST Alok Doshi Anand Mudlapur

  2. Overview • Introduction to spectral testing • Previous work • Application of RADEMACHER – WALSH spectrum in testing and design of digital circuits • Spectral techniques for sequential ATPG • Spectral methods for BIST in SOC • Spectral Analysis for statistical response compaction during BIST • Modifying spectral TPG using selfish gene algorithm • Proposed improvements • Results

  3. Introduction Projection of time varying vectors in the frequency domain. PI1 : 11001100 PI2 : 11110000 PI3 : 00111100 PI4 : 01010101

  4. Basic idea • Meaningful inputs (e.g., test vectors) of a circuit are not random. • Input signals must have spectral characteristics that are different from white noise (random vectors). • Sequential circuit tests are not random: • Some PIs are correlated. • Some PIs are periodic. • Correlation and periodicity can be represented by spectral components, e.g., Hadamard coefficients.

  5. Statistics of Test Vectors 100% coverage test Test vectors are not random: • Correlation: a = b, frequently. • Weighting: c has more 1s than a or b. a a 00011 b 01100 c 10101 b c

  6. Primary Motivation • We want to extract the information embedded in the input signals and output responses • Hence, we apply signal processing techniques to extract this information • In order to meet the above objective, we make use of frequency decomposition techniques. i.e. A signal can be projected to a set of independent, periodic waveforms that have different frequencies. • This set of waveforms, forms the basis matrix

  7. Primary Motivation (cont.) • The projection operation reveals the quantity that each basis vector contributes to the original signal • This quantity is called decomposition coefficient • With the aid the decomposed information, one can easily enhance the important frequencies and suppress the unimportant ones • This process leads us to a new and better quality signal, easing the complexity (in our case i.e. of test generation)

  8. Hadamard Transform • The projection matrix choosen is the Hadamard transform as it is a well-known non-sinusoidal orthogonal transform used in signal processing. • A Hadamard matrix consists of only 1’s and -1’s, which makes it a good choice for the signals in VLSI testing (1 = logic 1, -1 = logic 0). Each basis (row/column) in the Hadamard matrix is a distinct sequence that characterizes the switching frequency between 1s and -1s.

  9. Hadamard Transform (cont.) • Hadamard matrices are square matrices containing only 1s and –1s. They can be generated recursively using the formula, where, H(0) = 1 and n = log2N

  10. Hadamard Transform (cont.)

  11. Hadamard transforms over FFT • The Walsh functions can be interpreted as binary (sampled) versions of the sin and cos, which are the basic functions of the Discrete Fourier Transform. • This interpretation led to the name BInary FOurier REpresentation (BIFORE). • The inverse Hadamard transform is given by the transpose of the Hadamard matrix scaled by the factor 1/N.

  12. Hadamard transforms over FFT (cont.) • The flow graph of the Hadamard transform is shown below: x[0] X[0] x[1] X[1] The above flow graph resembles the radix-2 decimation-in-frequency FFT But it must be observed that Hadamard transform has no twiddle factors since its basis functions are square waves of either 1 or -1. Hence the Hadamard transform requires no multiplications and only N log (N) additions

  13. Applying spectral techniques to generate vectors for a sequential circuit [ Agrawal et al. `01] Replace with compacted vectors Test vectors (initially random vectors) Fault simulation-based vector compaction Compacted vectors Append new vectors Stopping criteria (coverage, CPU time, vectors) satisfied? Yes Stop Extract spectral characteristics (e.g., Hadamard coefficients) and generate vectors No

  14. Applying spectral techniques to generate vectors for a sequential circuit (cont.) • In seq. circuits, faults may need a biased input value • Static compaction is used to aid test generation. The resulting vector set has to retain the fault coverage • Vectors are appended before every iteration and static compaction is performed to remove the unwanted vectors that were appended

  15. Applying spectral techniques to generate vectors for a sequential circuit (cont.) • Initially the test set consists of random vectors • Static compaction filters all unnecessary vectors • Now the predominant patterns are identified at the inputs using the spectral information using the Hadamard transform. • New vectors are generated based on the information obtained • Using this process, one can traverse the vector space only using the basis vectors

  16. Applying spectral techniques to generate vectors for a sequential circuit (cont.) • This is of particular interest, since it drives the circuit to hard-to-reach states that require specific vectors at the PIs, making it easier to detect hard-to-detect faults • Each row/column in a Hadamard matrix is a basis vector, carrying a distinct frequency component. • Consider H(2) for example; the four basis vectors are [1 1 1 1], [1 0 1 0], [1 1 0 0], and [1 0 0 1] • Any bit sequence of length 4 can be represented as a linear combination of these basis vectors

  17. Applying spectral techniques to generate vectors for a sequential circuit (cont.) • Ex: [1 0 0 0] -1 x [ 1 1 1 1] + 1 x [ 1 -1 1 -1] + 1 x [1 1 -1 -1] + 1 x [1 -1 -1 1] • Ex: [1 1 1 0] +1 x [ 1 1 1 1] + 1 x [ 1 -1 1 -1] + 1 x [1 1 -1 -1] - 1 x [1 -1 -1 1]

  18. Applying spectral techniques to generate vectors for a sequential circuit (cont.) Let a, be the input bit sequence forprimary input i. for (each primary input i in test set) coefficient vector ci= H x ai for (each value in the coefficient matrix [c0, ..., cn]) if (absolute value of coefficient < cutoff) Set the coefficient to 0. else Set the coefficient to 1 or -1, based on its abs value. for (each primary input i) extension vector ei= modified ci x H if (weight > 0) Extend the vector set with value 1 to PI i. else if (weight < 0) Extend the vector set with value -1 to PI i. else if (weight == 0) Randomly extend the vector set with either 1 or -1

  19. Applying spectral techniques to generate vectors for a sequential circuit (cont.) Cut-off = 4 [0 1 0 0 0 0 0 0] x H(3) = [1 -1 1 -1 1 -1 1 -1]

  20. Applying spectral techniques to generate vectors for a sequential circuit (cont.) Cut-off = 4

  21. Applying spectral techniques to generate vectors for a sequential circuit (cont.) Faults detected per iteration for b12 benchmark circuit

  22. To be continued on Tuesday 11/16 …..

  23. Spectral Methods for BIST in a SOC environment [ A. Giani et al. `01] • This method of built-in-self-test (BIST) for sequential cores on a system-on-a-chip (SOC) generates test patterns using a real-time program that runs on an embedded processor. • This method resulted in higher fault coverage compared to the LFSR based random pattern generation techniques, without incurring the overhead of additional test hardware.

  24. Spectral Methods for BIST in a SOC environment (cont.)

  25. Random pattern generation with Selfish Gene algorithm for testing digital sequential circuits [ J. Zhang et al. ITC `04] • A selfish gene (SG) algorithm differs from the genetic algorithm (GA) because it evolves genes (characteristics) that provide higher fitness rather than evolving individuals with higher fitness. • The objects of evolution are the Hadamard spectral matrix, non-linear digital signal processing (DSP) filtering cutoff values, vector holding time, and relative input phase shifts, which are all modeled as genes.

  26. Random pattern generation with Selfish Gene algorithm for testing digital sequential circuits (cont.) Holding theorem

  27. Random pattern generation with Selfish Gene algorithm for testing digital sequential circuits (cont.) Phase Shifting

  28. Random pattern generation with Selfish Gene algorithm for testing digital sequential circuits (cont.) Original Sequence Phase shift of 1 I1 is the fault propagation sequence

  29. Random pattern generation with Selfish Gene algorithm for testing digital sequential circuits (cont.) • Step 1: On the first iteration, generate random vectors and compact them, but on subsequent iterations, use the compacted test sequence of the last iteration. • Step 2: In all algorithms for each vector in the compacted sequence, randomly generate a vector holding time between 0 and 64 and hold the vector accordingly to extend the sequence. If the holding time is 0, discard the vector. Holding a vector for some clock cycles is very important for high fault coverage. Further expand the test sequence. • Step 3: Evolve the genotype using the expanded sequence to get better fault coverage. • Step 4: Fault simulate and compact the best sequence. If the fault coverage is satisfactory or 125 iterations are finished, stop. Otherwise, iterate. Basic Algorithm

  30. Random pattern generation with Selfish Gene algorithm for testing digital sequential circuits (cont.) • Step 2: Hold vectors to form a new sequence Snew. After that, the following procedure is performed 50 times: { Generate a random perturbation ε in the range (-0.05; +0.05) for each bit i in the original sequence. Flip each bit with pi + ε > 0.5. Do this twice, to generate two new sequences, S1 and S2, which are fault-simulated. The winning sequence has the highest fault coverage. Change the bit-flipping probabilities in the gene. If the bit was flipped (not flipped) in both the winner and the loser, there is no change. If it flipped in the winner but not in the loser, pi = pi+0.01, otherwise pi = pi – 0.01}. Finally, only the bit with highest pi in each 8-bit chunk of each PI bit stream is flipped, provided that its pi > 0.5 (only one flip/chunk). This sequence becomes the extended sequence Snew. • Step 3: The final probabilities pi as evolved in Step 2 are discarded and reset to 0.5 for the next round of holding and perturbation. Bit – perturbation and selfish gene algorithm

  31. Spectral analysis for Statistical Response Compaction during BIST [ O. Khan et al. ITC `04] • Five new spectral response compactors SRC1-5 are presented. • The Hadamard matrix H(1) is used to perform spectral analysis. • Each of the SRC’s calculate either the auto-correlation of testing responses at primary outputs (POs) with the two spectral tones, each a row in H(1), or the cross-correlation between different POs. • The response compactors store the correlation coefficients, i.e., the spectral content in terms of the tones in H(1), in two counters, which represent the BIST signature.

  32. Spectral analysis for Statistical Response Compaction during BIST (cont.) Hadamard matrix H(1) used for spectral analysis

  33. Spectral analysis for Statistical Response Compaction during BIST (cont.) PO1 Add: 4 (1+1+0+1+1+0) Sub: 0 (-1+1+0-1+1+0)

  34. Spectral analysis for Statistical Response Compaction during BIST (cont.) 0 1 0 1 1 1 SRC1 101011 0 0 1 0 1 0 0 1 1 1 1 0 0 0 1 1 0 1 1 0

  35. Spectral analysis for Statistical Response Compaction during BIST (cont.) • SRC1 has higher area overhead compared to a MISR. • It was found that SRC1 was completely free of aliasing. • Holding test vectors for a number of clock cycles can improve the fault coverage in sequential circuits, but can potentially cause aliasing in a MISR.

  36. Spectral analysis for Statistical Response Compaction during BIST (cont.) SRC2

  37. Spectral analysis for Statistical Response Compaction during BIST (cont.) • This technique has a much lower area overhead than SRC1, since there is only one counter for the entire circuit, rather than one counter for each PO. • SRC2 has a slightly higher aliasing rate than the MISR.

  38. Spectral analysis for Statistical Response Compaction during BIST (cont.) • To reduce hardware overhead, the subtract counter and the hardware associated with it was eliminated from SRC1, and only the first spectral tone was used in SRC3. It was observed that the aliasing probability for SRC3 was higher than for SRC1. The hardware overhead for SRC3 is slightly less than that for SRC1. • SRC4 is identical to SRC3 except that the second spectral tone from SRC1 was implemented instead of the first. The overhead is slightly higher than for SRC3 because a subtracter requires an extra inverter.

  39. Spectral analysis for Statistical Response Compaction during BIST (cont.) SRC5

  40. Spectral analysis for Statistical Response Compaction during BIST (cont.) Hadamard Transform (HT) block

  41. Spectral analysis for Statistical Response Compaction during BIST (cont.) Causes of aliasing in SRC’s :- • Counter overflow; n = [log2(Length of test set)] • Bit flipping;

  42. Spectral analysis for Statistical Response Compaction during BIST (cont.) • They have used Upadhyayula’s method to design a spectral TPG, the basic idea of which is to hold vectors at PI’s of circuits for multiple clocks to increase fault coverage. • This new spectral BIST system has a 91.26% shorter test sequence than for a conventional LFSR pattern generator and MISR system, with at least 8.24% higher fault coverage.

  43. Proposed BIST scheme • Design of TPG • Response Compactor • MISR • Spectral compaction [Bushnell et al.] T P G CUT M I S R

  44. Proposed BIST scheme (cont.) x [ 1 1 -1 1] 1 1 1 1 [ 2 -2 2 2] 1 -1 1 -1 = 1 1 -1 -1 1 -1 -1 1

  45. Proposed BIST scheme (cont.) 0 X[0] 1 x[0] 2 -2 2 X[1] 1 x[1] -1 X[2] 2 -1 x[2] 2 -1 X[3] 2 1 x[3] 0 -1 -1

  46. Proposed BIST scheme (cont.) x[0] x[1] x[2] x[3] CUT

  47. Thank You