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Project Presentation for ELE6306 (Test des Circuits Electronics). Deterministic BIST. By Amiri Amir Mohammad Professor Dr. Abdelhakim Khouas. Deterministic BIST. Schemes To Discuss I. DBIST Schemes Based On Reseeding of LFSR A. General DBIST Scheme

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## Deterministic BIST

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**Project Presentation for ELE6306 (Test des Circuits**Electronics) Deterministic BIST By Amiri Amir Mohammad Professor Dr. Abdelhakim Khouas Ecole Polytechnique**Deterministic BIST**• Schemes To Discuss • I.DBIST Schemes Based On Reseeding of LFSR • A. General DBIST Scheme • B. Implicit Encoding (Re-ordering Of Patterns) • C. Implicit Encoding(Reordering 2Of Test cubes+ next-bit) • II.DBIST Schemes Using Internal Patterns • A. Bit-Flipping BIST (BFF) • B. Improved BFF BIST (SMF) • III.Others • SMF with Multiple Scan • DBIST with TPI Ecole Polytechnique**BIST OVERVIEW**• PRPG • Random patterns by LFSR with P(x) • Signature Analysis by MISR • Large number of Patterns to achieve FC • Delay & performance issues • Deterministic • Complex Algorithms • Increased Complexity for larger and complex circuits • Many patterns needed to achieve desired FC • Delay and Costly Ecole Polytechnique**Deterministic BIST**• What? • Improved BIST scheme • Why? • Increase FC in Scan-Based Design • Improve test application time and performance • How? • Random Patterns + Deterministic • Initiallyrandom patterns • Generated by Internal LFSR • Random resistant faults not detected • Followed by Deterministic Patterns • Generated by ATPG • Tend to detect hard-to-detect faults (random resistant) Ecole Polytechnique**I. DBIST (LFSR Reseeding)**• A. General Scheme • k-bit MP-LFSR Programmable • 2k distinct patterns • x primitive polynomials => x different sequences of patterns depending on initial value (seed) • ATPG-generated deterministic pattern encoded into n-bit word • q-bit => Poly. Id (2qPolynomials) • (n- q) bit => LFSR seed • m-bitScan Register Ecole Polytechnique**I. DBIST (LFSR Reseeding)**• Behavior • LFSR loaded with seed value • Poly ID identifies FeedBack configuration • LFSR output bits serially shifted into the Scan Register in m-clocks • Generated pattern consistent with encoded deterministic pattern • Original Test Cube - - 0 0 - - - 1 - 0 • Generated pattern 1 1 0 0 101 1 0 0 Ecole Polytechnique**I. DBIST (LFSR Reseeding)**• Encoding Of Test Cubes • Size of seed depends on number of carebitsin Test Cube C • carebit=> specified bit either 1 or 0, not‘x’ • A set of test cubesT = { C1, C2,…, Ci } • S(Ci) = { indice of carebits in test cube Ci} • s(Ci) = Number of carebits in test cube Ci • smax(T) = maximum number of specified bits in set T • Example: T={ C1 , C2 , C3 } • C1 = x1xx0x11xx , C2 = xxx10xx1xx, C3 = 0x1xxxx0xx • S(C1) = {2 , 3 , 5 , 8} s(C1)=4s(C2)=3 s(C3) = 3smax(T) = 4 • aiconsistentwithci • * ci = ai = (a(0). Mi )1 = (a(0).Mi-k+1 )k • Companion matrixM Ecole Polytechnique**I. DBIST (LFSR Reseeding)**• Encoding Of Test Cubes (continued..) • To encode C into a seed a • Solvings(C)system of non-linear equations in terms of seed variables(a0, …, ak-1) & polynomial coefficients (p0,…,pk-1 ), obtained from * • Two way to solve: • 1. Fixing seed variables, and finding the corresponding P(x) • System of non-linear equations (complex to solve) • 2. Fixing P(x), and finding seed variables • Simpler to solve • Less computation time in general • If no solution with P1(x), choose next polynomial • average # of polynomials analyzed slightly greater than one Ecole Polytechnique**I. DBIST (LFSR Reseeding)**• (M i-k+1 )kCalculated for each i and k • Subscript k indicates kthposition in the set of seed variablesa(0) • Example:GivenP (x) = x4 + x3 + 1 • p0=1 p1=0 p2=0 p3=1 • C = “x 1xx 0xx 11x” => S(C) = {1,2,5,8} and s(C) = 4. • For each index i in S(C), calculate a(0). Mi Ecole Polytechnique**I. DBIST (LFSR Reseeding)**• Only 4-bit encoding for 10 bit test cube • (4 + q)-bit stored in Memory Ecole Polytechnique**I. DBIST (LFSR Reseeding)**• General Scheme • Efficient Encoding • Probabilistic Analysis show Very high probability of successfull encoding with s + 4 bits ( 16 polynomial LFSR ) • Area Overhead • N Patterns => N x (s + q) bits of storage • Control Logic For configuration • Optimization possible in terms of storage area Ecole Polytechnique**I. DBIST (LFSR Reseeding)**• B. Implicit Encoding Scheme (1) • Modified Reseeding Scheme • Re-ordering of Test Cubes • Reduced Storage Size • No storage for poly id • Periodic Operation • Mod-p counter • p is the period of the sequence of polynomials (p feedback polynomials) • Addition of Random Patterns to complete periods • High Computational Effort Ecole Polytechnique**I. DBIST (LFSR Reseeding)**• B. Implicit Encoding Scheme (1) (Continued..) • Periodic Operation Example: • T = {C1, C2, C3, C4} & set of PolynomialsP(C)whereP (Ci)contains all the polynomials that can generateCi • P (C1) = {p1, p4}, P (C2) = P (C3) ={p1, p2, p3, p4} P (C4) ={p2, p3} • p1andp2can generate all the patterns • (C1, C2) by p1 ; (C3, C4) by p2 • Therefore: ( C1, C2, C3, C4 ) Implies Sequence of Polynomials (p1, p1, p2, p2) • Re-ordering : (p1, p2, p1, p2) => ( C1, C3, C2, C4 ) minimum period2 • adding random patternsto make perfect ordering not necessary (i.e counter can be stopped in last period at any time) • Can insert more polynomial from P(Ci) at the expense of AREA Ecole Polytechnique**I. DBIST (LFSR Reseeding)**• B. Implicit Encoding Scheme (1) (Continued..) • Issue: • achieve a re-ordering of the polynomials such that all the test cubes are covered, and so by having a sequence of polynomials with minimum period • Therefore: Need An Algorithm to reduce the list of test cubes generated by each polynomial and hence reduce period • TestCubeCompaction • To improve time of test application and the efficiency of encoding • Techniques • Simplification : Removal of Ci from T if Ci is a subsets of Cj • Merging : consistent test cubes combined such that s(mrg(C1C2…Ci))≤ s(T) is met. • Concatenation : Ci&Cj&…&Cz if s(concat(..))≤ s(T) Ecole Polytechnique**I. DBIST (LFSR Reseeding)**Ecole Polytechnique • B. Implicit Encoding Scheme (1) (Continued..) • TestCube Compaction (Example): • Simplification And Merging**I. DBIST (LFSR Reseeding)**• Only 3 encoding needed as opposed to 4. • Therefore, Reduced Encoding and consequently improved time of test application can be obtained Ecole Polytechnique • B. Implicit Encoding Scheme (1) (Continued..) • TestCube Compaction (Example..): • Concatenation**I. DBIST (LFSR Reseeding)**• B. Implicit Encoding Scheme (2) • Modified Reseeding Scheme • Re-ordering of Test Cubes • Reduced Storage Size • Seed grouping • Storage required for Next-bit • q-bit counter • Each state of Counter correponds to a feedback configuration • No Balancing needed in the number of seeds • (smax + 1) x N storage for N patterns Ecole Polytechnique**II. DBIST Scheme Using Internal Patterns**• A. Bit Flipping BIST (BFF) (Continued..) • Pattern mapping • Useless random patterns converted intodeterministic • BFF block is combinational and responsible to flip an output bit of LFSR at particular states of LFSR Ecole Polytechnique**II. DBIST Scheme Using Internal Patterns**• A. Bit Flipping BIST (BFF) (Continued..) • Efficient Mapping • Pr and Pd with minimumhumming distance • Minimumcost (least number of minterms) • Random PatternPr • Pr = f ( LFSR states) • On-set(Pr): Modifiable bits • Off-set(Pr): fixed bits (consistent with Pd ) • Fix-set: • On-, Off-, Fix-setscontainLFSR states • {s0, s1, …, s k-1} Ecole Polytechnique**II. DBIST Scheme Using Internal Patterns**• A. Bit Flipping BIST (BFF) (Continued..) • BFFfunction • Constructed iteratively starting with BFF0 ending with BFFR in R iterations • At each iterationr (0 ≤ r ≤ R ) • New Pd embeded in BFF • More Hard-to-detect faults coverd • New set of Hard-to-detect faults F identified • Final BFFR covers all faults • Fix0set of LFSR states, whose random patterns detect some faults Ecole Polytechnique**II. DBIST Scheme Using Internal Patterns**• A. Bit Flipping BIST (BFF) (Continued..) • Example: 3-bit LFSR, 5-bit Scan Register, F = {f1, f2, f3, f4, f5}, primitiveP (x) generating s0-s6 as below. • Assume P1 = 11xxx and P2 = 0xx1x Covering f1, f2, f3 • Fix1={s5, s6}Fix2={s3, s6}and Fix0 = Union(Fix1, Fix2} = {s3 , s5 , s6 } • BFF0 = Ø and Fix0 = {s3 , s5 , s6 } • A determinstic pattern Pd = 11 x 01 covering f4, f5 • Hence, need to mapPdonto a Pr in the list Ecole Polytechnique**II. DBIST Scheme Using Internal Patterns**• A. Bit Flipping BIST (BFF) (Continued..) • Example (cont..): • on-set and off-set for all Pr w.r.t (Pd = 11 x 01) • Candidates for mapping Pd:P1, P2, P4. Why notP3, P5? P1 chosen, because minimumcost (humming distance + least # of minterms ) • NewBFF= Union {BFF0, on-set (Pd, P1)} = { s0 } • NewFIX = FIX1 = Union {FIX0, on-set (Pd , P1), off-set (Pd , P1)} = {s0, s1, s3, s4, s5, s6} Ecole Polytechnique**II. DBIST Scheme Using Internal Patterns**• A. Bit Flipping BIST (BFF) (Continued..) • MinimizingBFF by considering s0 (on-set elements) only • New LFSR patterns => • Pd = 11 x 01 • P1=11xxxP2=0xx1x • Randomly modified Ecole Polytechnique**II. DBIST Scheme Using Internal Patterns**• B. Improved BFF (SMF) • Extension of BFF • Improves Area Overhead • Autocorrelation between random patterns • 1111- 0111-1011-1101-1110 • SMF = f ( LFSR states, Bit-counter bits, Pattern-counter bits) • Same procedure as BFF to get SMF function, exceptstate variables are different Ecole Polytechnique**II. DBIST Scheme Using Internal Patterns**• B. Improved BFF (SMF) (continued..) • Example: Given 2-bit LFSR with P(x) with states as below, test length 6, 5-bit Scan Register, and need to generate • Pd1 = “00010 , Pd2 = “00011 • Looking at the table • Minimum of 2 bits need to be modified for a chosen Pr Ecole Polytechnique**II. DBIST Scheme Using Internal Patterns**• B. Improved BFF (SMF) (continued..) • Example(continued.. ) • Pd1, Pd2 are similar • Pd1 maps onto P1(minimum cost) • On1 ( Pd1 , P1 )= { 000 000 01, 010 000 01} • Off1 ( Pd1 ,P1 )={ 001 000 10, 011 000 01, 100 000 10} • logic minimization similar to BFF • SMF1= {xx0 xxx x1} • covering all terms of On1 ( Pd1 , P1 )but none of Off1 ( Pd1 ,P1 ) • Fix1=Union{ On1 ( Pd1 , P1 ), Off1 ( Pd1 ,P1 )} • To map Pd2, repeated P1 (P4) is the candidate Ecole Polytechnique**II. DBIST Scheme Using Internal Patterns**• B. Improved BFF (SMF) (continued..) • SMF1: • With the new table, only 1-bit modification possible for mapping Pd2 • On2( Pd2 , P4)= {100 011 10} • Off 2(Pd2 , P4) = {000 011 01, 001 01110, 010 011 11, 011 011 01}and FIX2 = Union { Fix1, Off 2(Pd2 , P4), On2( Pd2 , P4)} • SMF2= {xx0 xxx x1, xx0 xx1 xx}=b0. (p0 + t0) Ecole Polytechnique**II. DBIST Scheme Using Internal Patterns**• B. Improved BFF (SMF) (continued..) • SMF2: • Pd1and Pd2 mapped efficiently with only two minterms Ecole Polytechnique**II. DBIST Scheme Using Internal Patterns**• B. Improved BFF (SMF) (continued..) • Efficiency of the SMF over PRPG • High FC compared to PRPG for • Less Area than the 32-bit register used for PRPG for the same FC • Less Area than BOTH (BFF and General) Ecole Polytechnique**III. OthersSchemes**• SMF with Multiple Scan • Improvement over single-scan SMF • Breaking one large scan register into several scan registers • Reduced time of test application (less FFs) • Similar Synthesis process as single scan SMF , except at logic minimization step • Patterns feed several scan paths • Pd can map onto any path Ecole Polytechnique**III. OthersSchemes**• DBIST Schemes • DBIST with TPI • BFFcombined with TPI (Test point insertion) • Improves • Random testability • Controllability and Observability • 100% FC achieved with less area Ecole Polytechnique**VI. Conclusion**• DBIST Schemes • Reseeding of LFSR • General DBIST Scheme • High FC • Efficient Encoding ( Less computational effort for encoding of seeds) • Storage Area Overhead (seed + poly id ) • Implicit Encoding (1) • High FC • Less Storage Area ; mod-p counter needed • More Computational effort needed for encoding of seeds • Re-ordering needed + added Random Patterns for balancing • Implicit Encoding (2) • High FC • next-bit + p-bit counter (for p polynomials of LFSR) • No balancing problem, hence no random patterns need to be added Ecole Polytechnique**VI. Conclusion**• DBIST Schemes • Internal Pattern Generation • BFF • High FC • Pattern Mapping • Less Area Overhead (No Storage required) • Synthesis process • SMF (single scan design) • High FC • Pattern Mapping • Furthre improve BFF for area overhead ( reduced-size LFSR ) • Synthesis Process • SMF with Multiple Scan Register • improved time of test Application Ecole Polytechnique**Questions?**Ecole Polytechnique

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