microprocessor system architectures ia32 paging
Download
Skip this Video
Download Presentation
Microprocessor system architectures – IA32 paging

Loading in 2 Seconds...

play fullscreen
1 / 25

Microprocessor system architectures – IA32 paging - PowerPoint PPT Presentation


  • 123 Views
  • Uploaded on

Microprocessor system architectures – IA32 paging. Jakub Yaghob. Control – global setting. Paging modes. Address translation – 4K pages , 32-bit physical address. Address translation – 4 M pages , 32-bit physical address. Page Directory – 4K/32b. Page Table – 4K/32b.

loader
I am the owner, or an agent authorized to act on behalf of the owner, of the copyrighted work described.
capcha
Download Presentation

PowerPoint Slideshow about 'Microprocessor system architectures – IA32 paging' - amos


An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript
pae page address extension
PAE – Page Address Extension
  • Widens possibility of addressing physical memory to 36 bits (64GB)
  • Available from Pentium Pro
  • Paging data structures changed
    • Other release of OS (different compilation)
    • PDBR changed
  • Bit NX (No eXecute)/XD (eXecution Disabled)
    • NewerAMD/Pentium 4
pse 36 page size extension 36 bit
PSE-36 – Page Size Extension 36-bit
  • An alternate method to the PAE
  • Allows addressing of 36 bits physical address space using 4M pages
  • Available fromPentium III
  • Only whenPSE-36 flag available (CPUID[17])
page fault
Page fault
  • All paging problems caught by #PF exception
    • Flag P set to 0
    • Access rights violation
  • Page table or page directory
protection
Protection
  • U/S flag
    • =0 – supervisor mode
      • CPL 0-2
    • =1 – user mode
      • CPL 3
  • R/W flag
    • =0 – read-only
      • Not used insupervisor mode, until flagWP (CR0[16]) is set
    • =1 – read/write
  • NX/XD flag
    • =0 – can execute
    • =1 – no execute
tlb translation lookaside buffer
TLB – Translation Lookaside Buffer
  • Associative memory for accelerating translation from linear to physical address
  • TLB purging
    • Explicitly usingmovcr3,eax
    • Implicitly during task change – reading new CR3
    • Entries with G flag set are not purged when PGE is set (CR4[7])
  • Selective entry purging
    • InstructionINVLPG
pae in long mode
PAE in long mode
  • Max limits
    • 64-bit linear address
    • 52-bit physical address
  • Current implementation
    • 48-bit linear address
    • 40-bit physical address
  • Setting
    • PAE must be enabled before switching to long mode
ad