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  1. EE384x: Packet Switch Architectures Handout 1: Logistics and Introduction Professor Balaji Prabhakar balaji@isl.stanford.edu Professor Nick McKeown nickm@stanford.edu EE384x Handout 1

  2. Outline This two course sequence is about the theory and practice of designing packet switches and Internet routers. • Introduction: What is a packet switch? The evolution of Internet routers, their basic architectural components, and some example architectures. • Part I: Output Queued Switches (Emphasis on Deterministic Analysis)OQ as the simplest and ideal architecture.Output queueing and shared-memory switches. Packet arrival processes: (s,r)-constrained arrivals, leaky buckets, Bernoulli arrivals, bursty arrivals, adversaries.Providing bandwidth and delay guarantees, scheduling, fairness, Fair-Queueing, Generalized Processor Sharing and Deficit Round Robin.Practical difficulties: When output queued switches are impractical.Memory bandwidth and capacity scaling. Some approaches: Emulating output queued switches. Parallel packet buffers as standalone shared memory, with design examples. Routers with a single stage of buffering and constraint sets, Parallel Shared Memory Routers, Distributed Shared Memory Routers, and Parallel Packet Switches. Output link scheduling in a Distributed Shared Memory router. Combined input and output queued (CIOQ) switches, stable marriage matchings. EE384x Handout 1

  3. Outline • Part II: Input Queued Switches (Emphasis on Probabilistic Analysis).What is an input-queued (IQ) switch?Definition of IQ switch with single FCFS queue. Switching fabrics, crossbars. Head of line blocking. The balls and bins model. Proof of Karol's 2-sqrt(2) (58%) result. Virtual output queues and crossbar schedulers. Bipartite Matchings: Maximum Sized Matchings, Maximum Weight Matchings, maximal matchings. Definitions of 100% throughput. When traffic is uniform: simple RR and random matchings. When traffic matrix is known: Birkhoff- von Neuman decomposition. When traffic is not known: heuristics. PIM, iSLIP, WFA. • Fundamentals (Review Sessions): Introduction to probability, Poisson process, Discrete and Continuous-time Markov chains. Basic queueing theory: M/M/1, M/G/1, Little’s result, PASTA. EE384x Handout 1

  4. Outline EE384y • Part II: Input Queued Switches (Continued).Intro to Lyapunov functions, proof that max weight matching gives 100% throughput.Some case studies: The Tiny Tera architecture. The Cisco GSR 12000. • Part III: Other Switch ArchitecturesBuffered crossbars. Scaling crossbars and parallelism. Multistage switches: Clos networks, 2-stage switches (random and deterministic). • Part IV: Other Switch FunctionsAddress Lookup: Exact matches, longest prefix matches, performance metrics, hardware and software solutions. Packet Classification: For firewalls, QoS, and policy-based routing; graphical description and examples of 2-D classification, examples of classifiers, theoretical and practical considerations. • Special topics. • Project presentations. EE384x Handout 1

  5. Some logistics Web page: http://www.stanford.edu/class/ee384x Course assistant: Denise Murphy – denise@ee.stanford.eduPackard 267; Tel: (650) 723-4731 TAs: Mohsen Bayati bayati@stanford.edu Nandita Dukkipati nanditad@stanford.edu Grades: You need to sign up with “eeclass” on the EE384x web page. EE384x Handout 1

  6. More Logistics Prerequisite • EE284/CS244A and familiarity with probability. Useful • Stats 116 (or EE178, EE278) and CS161 Papers • URLs to all the papers are on the eeclass web page. Grading • (40%) 5 Problem sets • (10%) Several surprise quizzes • (20%) In-class midterm exam (February 21) • (30%) Final exam (Thursday March 23, 3:30 - 6:30 PM) SITN Students • Same schedule as in-class students • Fax your assignment to us: (650) 618-1938 All deadlines are hard! EE384x Handout 1

  7. An IntroductionThe class starts here! Background • What is a router? • Why do we need faster routers? • Why are they hard to build? Architectures and techniques • The evolution of router architecture. • IP address lookup. • Packet buffering. • Switching. EE384x Handout 1

  8. D R3 R1 R4 D A B E R2 C R5 Destination Next Hop F D R3 E R3 F R5 What is Routing? EE384x Handout 1

  9. R3 R1 R4 D A 1 4 16 32 D Ver HLen T.Service Total Packet Length Fragment ID Flags Fragment Offset B E TTL Protocol Header Checksum 20 bytes Source Address R2 C R5 Destination Address Destination Next Hop F D R3 Options (if any) E R3 Data F R5 What is Routing? EE384x Handout 1

  10. R3 R1 R4 D A B E R2 C R5 F What is Routing? EE384x Handout 1

  11. POP3 POP2 POP1 D POP4 A B E POP5 POP6 C POP7 POP8 F Points of Presence (POPs) EE384x Handout 1

  12. Where High Performance Routers are Used (2.5 Gb/s) R2 (2.5 Gb/s) R1 R6 R5 R4 R7 R3 R9 R10 R8 R11 R12 R14 R13 R16 R15 (2.5 Gb/s) (2.5 Gb/s) EE384x Handout 1

  13. What a Router Looks Like Cisco GSR 12416 Juniper M160 19” 19” Capacity: 160Gb/sPower: 4.2kW Capacity: 80Gb/sPower: 2.6kW 6ft 3ft 2ft 2.5ft EE384x Handout 1

  14. Basic Architectural Componentsof an IP Router Routing Protocols Routing Table Control Plane Datapath per-packet processing Forwarding Table Switching EE384x Handout 1

  15. Per-packet processing in an IP Router 1. Accept packet arriving on an incoming link. 2. Lookup packet destination address in the forwarding table, to identify outgoing port(s). 3. Manipulate packet header: e.g., decrement TTL, update header checksum. 4. Send packet to the outgoing port(s). 5. Buffer packet in the queue. 6. Transmit packet onto outgoing link. EE384x Handout 1

  16. Data Hdr Data Hdr IP Address Next Hop Address Table Buffer Memory Generic Router Architecture Header Processing Lookup IP Address Update Header Queue Packet ~1M prefixes Off-chip DRAM ~1M packets Off-chip DRAM EE384x Handout 1

  17. Data Data Data Hdr Hdr Hdr Header Processing Header Processing Header Processing Lookup IP Address Lookup IP Address Lookup IP Address Update Header Update Header Update Header Address Table Address Table Address Table Data Data Hdr Hdr Data Hdr Generic Router Architecture Buffer Manager Buffer Memory Buffer Manager Buffer Memory Buffer Manager Buffer Memory EE384x Handout 1

  18. Why do we Need Faster Routers? • To prevent routers becoming the bottleneck in the Internet. • To increase POP capacity, and to reduce cost, size and power. EE384x Handout 1

  19. Why we Need Faster Routers 1: To prevent routers from being the bottleneck Packet processing Power Link Speed 10000 1000 2x / 18 months 2x / 7 months 100 Fiber Capacity (Gbit/s) 10 1 1985 1990 1995 2000 0,1 TDM DWDM Source: SPEC95Int & David Miller, Stanford. EE384x Handout 1

  20. POP with smaller routers • Ports: Price >$100k, Power > 400W. • It is common for 50-60% of ports to be for interconnection. Why we Need Faster Routers 2: To reduce cost, power & complexity of POPs POP with large routers EE384x Handout 1

  21. Why are Fast Routers Difficult to Make? • It’s hard to keep up with Moore’s Law: • The bottleneck is memory speed. • Memory speed is not keeping up with Moore’s Law. EE384x Handout 1

  22. 1.1x / 18 months Moore’s Law 2x / 18 months Why are Fast Routers Difficult to Make?Speed of Commercial DRAM • It’s hard to keep up with Moore’s Law: • The bottleneck is memory speed. • Memory speed is not keeping up with Moore’s Law. EE384x Handout 1

  23. Why are Fast Routers Difficult to Make? • It’s hard to keep up with Moore’s Law: • The bottleneck is memory speed. • Memory speed is not keeping up with Moore’s Law. • Moore’s Law is too slow: • Routers need to improve faster than Moore’s Law. EE384x Handout 1

  24. Router Performance Exceeds Moore’s Law Growth in capacity of commercial routers: • Capacity 1992 ~ 2Gb/s • Capacity 1995 ~ 10Gb/s • Capacity 1998 ~ 40Gb/s • Capacity 2001 ~ 160Gb/s • Capacity 2003 ~ 640Gb/s Average growth rate: 2x / 18 months. EE384x Handout 1

  25. Outline Background • What is a router? • Why do we need faster routers? • Why are they hard to build? Architectures and techniques • The evolution of router architecture. • IP address lookup. • Packet buffering. • Switching. EE384x Handout 1

  26. CPU Buffer Memory Route Table CPU Line Interface Line Interface Line Interface Memory MAC MAC MAC Typically <0.5Gb/s aggregate capacity First Generation Routers Shared Backplane Line Interface EE384x Handout 1

  27. Fwding Cache Second Generation Routers CPU Buffer Memory Route Table Line Card Line Card Line Card Buffer Memory Buffer Memory Buffer Memory Fwding Cache Fwding Cache MAC MAC MAC Typically <5Gb/s aggregate capacity EE384x Handout 1

  28. Fwding Table Third Generation Routers Switched Backplane Line Card CPU Card Line Card Local Buffer Memory Local Buffer Memory Line Interface CPU Routing Table Memory Fwding Table MAC MAC Typically <50Gb/s aggregate capacity EE384x Handout 1

  29. Fourth Generation Routers/SwitchesOptics inside a router for the first time Optical links 100s of metres Switch Core Linecards 0.3 - 10Tb/s routers in development EE384x Handout 1

  30. Outline Background • What is a router? • Why do we need faster routers? • Why are they hard to build? Architectures and techniques • The evolution of router architecture. • IP address lookup. • Packet buffering. • Switching. EE384x Handout 1

  31. Header Processing Header Processing Lookup IP Address Lookup IP Address Update Header Update Header Address Table Address Table Lookup IP Address Lookup IP Address Lookup IP Address Address Table Address Table Address Table Generic Router Architecture Buffer Manager Buffer Memory Header Processing Buffer Manager Lookup IP Address Update Header Buffer Memory Address Table Buffer Manager Buffer Memory EE384x Handout 1

  32. IP Address Lookup Why it’s thought to be hard: • It’s not an exact match: it’s a longest prefix match. • The table is large: about 150,000 entries today, and growing. • The lookup must be fast: about 30ns for a 10Gb/s line. EE384x Handout 1

  33. 128.9.16.14 IP Lookups find Longest Prefixes 128.9.172.0/24 128.9.16.0/21 128.9.172.0/21 142.12.0.0/19 65.0.0.0/8 128.9.0.0/16 0 232-1 Routing lookup:Find the longest matching prefix (aka the most specific route) among all prefixes that match the destination address. EE384x Handout 1

  34. IP Address Lookup Why it’s thought to be hard: • It’s not an exact match: it’s a longest prefix match. • The table is large: about 150,000 entries today, and growing. • The lookup must be fast: about 30ns for a 10Gb/s line. EE384x Handout 1

  35. Source: http://www.cidr-report.org/ Address Tables are Large EE384x Handout 1

  36. IP Address Lookup Why it’s thought to be hard: • It’s not an exact match: it’s a longest prefix match. • The table is large: about 150,000 entries today, and growing. • The lookup must be fast: about 30ns for a 10Gb/s line. EE384x Handout 1

  37. Lookups Must be Fast Year Line 40B packets (Mpkt/s) 1997 622Mb/s 1.94 1999 2.5Gb/s 7.81 2001 10Gb/s 31.25 2003 40Gb/s 125 EE384x Handout 1

  38. Outline Background • What is a router? • Why do we need faster routers? • Why are they hard to build? Architectures and techniques • The evolution of router architecture. • IP address lookup. • Packet buffering. • Switching. EE384x Handout 1

  39. Header Processing Header Processing Header Processing Lookup IP Address Lookup IP Address Lookup IP Address Update Header Update Header Update Header Address Table Address Table Address Table Buffer Manager Buffer Manager Buffer Manager Buffer Memory Buffer Memory Buffer Memory Generic Router Architecture Queue Packet Buffer Memory Queue Packet Buffer Memory Queue Packet Buffer Memory EE384x Handout 1

  40. Fast Packet Buffers Example: 40Gb/s packet buffer Size = RTT*BW = 10Gb; 40 byte packets Write Rate, R Read Rate, R Buffer Manager 1 packet every 8 ns 1 packet every 8 ns Buffer Memory Use SRAM? + fast enough random access time, but - too low density to store 10Gb of data. Use DRAM? + high density means we can store data, but - too slow (50ns random access time). EE384x Handout 1

  41. Outline Background • What is a router? • Why do we need faster routers? • Why are they hard to build? Architectures and techniques • The evolution of router architecture. • IP address lookup. • Packet buffering. • Switching. EE384x Handout 1

  42. Data Data Data Hdr Hdr Hdr Header Processing Header Processing Header Processing Lookup IP Address Lookup IP Address Lookup IP Address Update Header Update Header Update Header Address Table Address Table Address Table N times line rate Generic Router Architecture 1 1 Queue Packet Buffer Memory 2 2 Queue Packet Buffer Memory N times line rate N N Queue Packet Buffer Memory EE384x Handout 1

  43. Data Data Data Data Data Data Hdr Hdr Hdr Hdr Hdr Hdr Header Processing Header Processing Header Processing Lookup IP Address Lookup IP Address Lookup IP Address Update Header Update Header Update Header 1 1 Address Table Address Table Address Table 2 2 N N Generic Router Architecture Queue Packet Buffer Memory Queue Packet Buffer Memory Scheduler Queue Packet Buffer Memory EE384x Handout 1

  44. A Router with Input Queues The best that any queueing system can achieve. EE384x Handout 1

  45. A Router with Input QueuesHead of Line Blocking The best that any queueing system can achieve. EE384x Handout 1

  46. Head of Line Blocking EE384x Handout 1

  47. Virtual Output Queues EE384x Handout 1

  48. A Router with Virtual Output Queues The best that any queueing system can achieve. EE384x Handout 1

  49. Maximum Weight Matching S*(n) L11(n) A11(n) D1(n) A1(n) 1 1 A1N(n) DN(n) AN1(n) AN(n) N N ANN(n) LNN(n) L11(n) Maximum Weight Match LN1(n) Bipartite Match “Request” Graph EE384x Handout 1

  50. Outline of Proof EE384x Handout 1