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Chapter 6 – MSP430 Micro-Architecture

Chapter 6 – MSP430 Micro-Architecture. Concepts to Learn…. Computer Architecture MSP430 Micro-Architecture Instruction Cycle Review Fetch Cycle Addressing Modes Operand Fetch Cycles Execute Cycle Store Cycle Instruction Clock Cycles Digital I/O. Levels of Transformation. Problems.

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Chapter 6 – MSP430 Micro-Architecture

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  1. Chapter 6 – MSP430Micro-Architecture

  2. Concepts to Learn… • Computer Architecture • MSP430 Micro-Architecture • Instruction Cycle Review • Fetch Cycle • Addressing Modes • Operand Fetch Cycles • Execute Cycle • Store Cycle • Instruction Clock Cycles • Digital I/O Chapter 6 - MSP430 Micro-Architecture

  3. Levels of Transformation Problems Algorithms Language (Program) Programmable Computer Specific Machine (ISA) Architecture Microarchitecture Manufacturer Specific Circuits Devices Chapter 6 - MSP430 Micro-Architecture

  4. Computer Architecture Computer Architecture Like a building architect, whose place at the engineering/arts and goals/means interfaces is seen in this diagram, a computer architect reconciles many conflicting or competing demands. Chapter 6 - MSP430 Micro-Architecture

  5. MSP430 Micro-Architecture MSP430 Modular Architecture Chapter 6 - MSP430 Micro-Architecture

  6. MSP430 Micro-Architecture Memory Organization Chapter 6 - MSP430 Micro-Architecture

  7. MSP430 Micro-Architecture Micro-Architecture Simulator Address Bus Program Counter Memory Address Register Source Operand Instruction Register Destination Operand Port 1 Output Memory Arithmetic Logic Unit Condition Codes Chapter 6 - MSP430 Micro-Architecture Data Bus

  8. Quiz… • Disassemble the following MSP430 instructions: AddressData 0x8010: 4031 0x8012: 0600 0x8014: 40B2 0x8016: 5A1E 0x8018: 0120 0x801a: 430E 0x801c: 535E 0x801e: F07E 0x8020: 000F 0x8022: 1230 0x8024: 000E 0x8026: 8391 0x8028: 0000 0x802a: 23FD 0x802c: 413F 0x802e: 3FF6 Chapter 6 - MSP430 Micro-Architecture

  9. Quiz… • Disassemble the following MSP430 instructions: AddressData 0x8010: 4031 0x8012: 0600 0x8014: 40B2 0x8016: 5A1E 0x8018: 0120 0x801a: 430E 0x801c: 535E 0x801e: F07E 0x8020: 000F 0x8022: 1230 0x8024: 000E 0x8026: 8391 0x8028: 0000 0x802a: 23FD 0x802c: 413F 0x802e: 3FF6 mov.w #0x0600,r1 mov.w #0x5a1e,&0x0120 mov.w #0,r14 add.b #1,r14 and.b #0x0f,r14 push #0x000e sub.w #0,0(r1) jne 0x8026 mov.w @r1+,r15 jmp 0x801c Chapter 6 - MSP430 Micro-Architecture

  10. Instruction Cycle The Instruction Cycle • INSTRUCTION FETCH • Obtain the next instruction from memory • DECODE • Examine the instruction, and determine how to execute it • SOURCE OPERAND FETCH • Load source operand • DESTINATION OPERAND FETCH • Load destination operand • EXECUTE • Carry out the execution of the instruction • STORE RESULT • Store the result in the designated destination Not all instructions require all six phases Chapter 6 - MSP430 Micro-Architecture

  11. PC  Fetch Cycle Fetching an Instruction Chapter 6 - MSP430 Micro-Architecture

  12. Addressing Modes Addressing Modes Chapter 6 - MSP430 Micro-Architecture

  13. Addressing Modes Source Addressing Modes • The MSP430 has four basic modes for the source address: • Rs - Register • x(Rs) - Indexed Register • @Rs - Register Indirect • @Rs+ - Indirect Auto-increment • In combination with registers R0-R3, three additional source addressing modes are available: • label - PC Relative, x(PC) • &label – Absolute, x(SR) • #n – Immediate, @PC+ Chapter 6 - MSP430 Micro-Architecture

  14. Addressing Modes MSP430 Source Constants • To improve code efficiency, the MSP430 "hardwires" six register/addressing mode combinations to commonly used source values: • #0 - R3 in register mode • #1 - R3 in indexed mode • #4 - R2 in indirect mode • #2 - R3 in indirect mode • #8 - R2 in indirect auto-increment mode • #-1 - R3 in indirect auto-increment mode • Eliminates the need to use a memory location for the immediate value - commonly reduces code size by 30%. Chapter 6 - MSP430 Micro-Architecture

  15. Addressing Modes Destination Addressing Modes • There are two basic modes for the destination address: • Rd - Register • x(Rd) - Indexed Register • In combination with registers R0/R2, two additional destination addressing modes are available: • label - PC Relative, x(PC) • &label – Absolute, x(SR) Chapter 6 - MSP430 Micro-Architecture

  16. Operand Fetch Cycles Register Addressing Mode Chapter 6 - MSP430 Micro-Architecture

  17. Rs  Operand Fetch Cycles Source: Register Mode – Rs Chapter 6 - MSP430 Micro-Architecture

  18. Rs  Operand Fetch Cycles Destination: Register Mode – Rd Chapter 6 - MSP430 Micro-Architecture

  19. Operand Fetch Cycles Register-Indexed Addressing Mode Chapter 6 - MSP430 Micro-Architecture

  20. Rs PC PC    Operand Fetch Cycles Source: Indexed Mode – x(Rs) Chapter 6 - MSP430 Micro-Architecture

  21. Operand Fetch Cycles Symbolic Addressing Mode Chapter 6 - MSP430 Micro-Architecture

  22. PC PC PC    Operand Fetch Cycles Source: Symbolic Mode – Address Chapter 6 - MSP430 Micro-Architecture

  23. Operand Fetch Cycles Absolute Addressing Mode Chapter 6 - MSP430 Micro-Architecture

  24. SR (0) PC PC    Operand Fetch Cycles Source: Absolute Mode – &Address Chapter 6 - MSP430 Micro-Architecture

  25. Operand Fetch Cycles Register Indirect Addressing Mode Chapter 6 - MSP430 Micro-Architecture

  26. Rs  Operand Fetch Cycles Source: Indirect Mode – @Rs Chapter 6 - MSP430 Micro-Architecture

  27. Operand Fetch Cycles Register Indirect Auto-increment Chapter 6 - MSP430 Micro-Architecture

  28. Rs Rs   Operand Fetch Cycles Source: Indirect Auto Mode – @Rs+ Chapter 6 - MSP430 Micro-Architecture

  29. Operand Fetch Cycles Immediate Addressing Mode Chapter 6 - MSP430 Micro-Architecture

  30. PC  Operand Fetch Cycles Source: Immediate Mode – #n Chapter 6 - MSP430 Micro-Architecture

  31. SP  SP  Execute Cycle Execute Phase: PUSH.W Chapter 6 - MSP430 Micro-Architecture

  32. Execute Cycle Execute Phase: Jump Chapter 6 - MSP430 Micro-Architecture

  33. Store Cycle Store Phase: Rd Chapter 6 - MSP430 Micro-Architecture

  34. Store Cycle Store Phase: Other… Chapter 6 - MSP430 Micro-Architecture

  35. Instruction Clock Cycles Instruction Timing • Instruction cycles = Power consumption • Most instruction cycles limited by access to memory (von Neumann bottleneck) • In general • 1 cycle to fetch instruction • +1 cycle for @Rn, @Rn+, or immediate • +2 cycles for indexed, absolute, or symbolic • +1 to write destination back to memory • 2 cycles for any jump • No difference between byte and word Chapter 6 - MSP430 Micro-Architecture

  36. Digital I/O Digital I/O • Digital I/O grouped in 8 bit memory locations called ports • Each I/O port can be: • programmed independently for each bit • combined for input, output, and interrupt functionality • Edge-selectable input interrupt capability for all 8 bits of ports P1 and P2 • Read/write access using regular MSP430 byte instructions • Individually programmable pull-up/pull-down resistors • The available digital I/O pins for the hardware development tools: • eZ430-F2013: 10 pins - P1 (8 bits) and P2 (2 bits); • eZ430-F2274: 32 pins – P1, P2, P3, and P4 Chapter 6 - MSP430 Micro-Architecture

  37. Digital I/O 8-bit Digital I/O Registers • Direction Register (PxDIR): • Bit = 1: the individual port pin is set as an output • Bit = 0: the individual port pin is set as an input • Input Register (PxIN): • When pins are configured as GPIO, each bit of these read-only registers reflects the input signal at the corresponding I/O pin • Bit = 1: The input is high • Bit = 0: The input is low • Output Register (PxOUT): • Each bit of these registers reflects the value written to the corresponding output pin. • Bit = 1: The output is high; • Bit = 0: The output is low. • Note: the PxOUT is a read-write register which means previously written values can be read, modified, and written back Chapter 6 - MSP430 Micro-Architecture

  38. Digital I/O Select Digital I/O Registers • Function Select Registers: (PxSEL) and (PxSEL2): • Port P2.0 Example: Chapter 6 - MSP430 Micro-Architecture

  39. Digital I/O Interrupt Digital I/O Registers • Interrupt Enable (PxIE): • Read-write register to enable interrupts on individual pins on ports P1/P2 • Bit = 1: The interrupt is enabled • Bit = 0: The interrupt is disabled • Each PxIE bit enables the interrupt request associated with the corresponding PxIFG interrupt flag • Interrupt Edge Select Registers (PxIES): • Selects the transition on which an interrupt occurs • Bit = 1: Interrupt flag is set on a high-to-low transition • Bit = 0: Interrupt flag is set on a low-to-high transition • Interrupt Flag Registers (PxIFG) • Set automatically when the programmed signal transition (edge) occurs • PxIFG flag can be set and must be reset by software • Bit = 0: No interrupt is pending • Bit = 1: An interrupt is pending Chapter 6 - MSP430 Micro-Architecture

  40. +3.3v P2.0 P2.1 P2.2 P2.3 P2.4 Digital I/O Pull-up/down Register • Pull-up/down Resistor Enable Registers (PxREN): • Each bit of this register enables or disables the pull-up/pull-down resistor of the corresponding I/O pin • Bit = 1: Pull-up/pull-down resistor enabled • Bit = 0: Pull-up/pull-down resistor disabled. • When pull-up/pull-down resistor is enabled, Output Register (PxOUT) selects: • Bit = 1: The pin is pulled up • Bit = 0: The pin is pulled down. Chapter 6 - MSP430 Micro-Architecture

  41. Digital I/O Port P1 Registers Chapter 6 - MSP430 Micro-Architecture

  42. Chapter 6 - MSP430 Micro-Architecture

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