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Chapter 2 Instructions: language of the Machine
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1. Chapter 2Instructions: language of the Machine 授課教師: 張傳育 博士 (Chuan-Yu Chang Ph.D.) E-mail: chuanyu@yuntech.edu.tw Tel: (05)5342601 ext. 4337

2. Instructions: • Language of the Machine • More primitive than higher level languagese.g., no complex control flow • Very restrictivee.g., MIPS Arithmetic Instructions • We’ll be working with the MIPS instruction set architecture • similar to other architectures developed since the 1980's • Almost 100 million MIPS processors manufactured in 2002 • used by NEC, Nintendo, Cisco, Silicon Graphics, Sony, … • Design goals: To find a language that makes it easy to build the hardware and compiler while maximizing performance and minimize cost, reduce design time

3. MIPS arithmetic • All instructions have 3 operands • Operand order is fixed (destination first) • \$s0, \$s1,… for registers that correspond to variables in C programs • \$t0, \$t1,… for temporary registers needed to compile the program into MIPS instruction. • Example:C code: A = B + CMIPS code: add \$s0, \$s1, \$s2 (associated with variables by compiler)

4. Examples • Compiling Two C Assignment Statements into MIPS • a = b + c;d = a – e; • Solutionadd a, b, csub d, a, e • Compiling a Complex C Assignment into MIPS • f = (g + h) – (i + j);Solutionadd t0, g, hadd t1, i, j sub f, t0, t1

5. MIPS arithmetic • Design Principle: simplicity favors regularity(簡單明瞭有助於一致性). • Example: C code: a = b + c + d; e = f - a; MIPS code: add \$t0, \$s1, \$s2 add \$s0, \$t0, \$s3 sub \$s4, \$s5, \$s0 • Operands must be registers, only 32 registers provided • Design Principle: smaller is faster. The variables a, b, c, d, e and f are assigned to the registers \$s0, \$s1, \$s2, \$s3, \$s4, \$s5. The size of a register in the MIPS architecture is 32 bits

6. Example • Compiling a C assignment Using Registers • f = (g + h) – (i + j);SolutionThe variables f, g, h, i, and j are assigned to the registers \$s0, \$s1, \$s2, \$s3, \$s4.The compiled MIPS code :add t0, \$s1, \$s2add t1, \$s3, \$s4 sub \$s0, \$t0, \$t1

7. Registers vs. Memory Control Input Memory Datapath Output Processor I/O • Arithmetic instructions operands must be registers, — only 32 registers provided • Compiler associates variables with registers • What about programs with lots of variables? • The CPU can keep only a small amount of data in registers. • Computer memory contains millions of data elements. • MIPS must include instructions (data transfer instruction) that transfer data between memory and registers..

8. Memory Organization 0 8 bits of data 1 8 bits of data 2 8 bits of data 3 8 bits of data 4 8 bits of data 5 8 bits of data 6 8 bits of data ... • How can a computer represent and access large memory? • Viewed as a large, single-dimension array, with an address. • A memory address is an index into the array • "Byte addressing" means that the index points to a byte of memory.

9. Memory Organization 0 32 bits of data 4 32 bits of data Registers hold 32 bits of data 8 32 bits of data 12 32 bits of data ... • Bytes are nice, but most data items use larger "words" • For MIPS, a word is 32 bits or 4 bytes. • 232 bytes with byte addresses from 0 to 232-1 • 230 words with byte addresses 0, 4, 8, ... 232-4 • Words are aligned

10. Instructions Base register offset • Load instructions • lw: (load word): moves data from memory to a register. • Store instructions • sw: (store word): transfers data from a register to memory • Store word has destination last • Example:Let’s assume that A is an array of 100 words and that the compiler has associated the variables g and h with the registers \$s1 and \$s2 as before. The starting address of the array is in \$s3. Translate this C assignment statement:C code: g = h + A MIPS code: lw \$t0, 32(\$s3)add \$s1, \$s2, \$t0 C code: A = h + A; MIPS code: lw \$t0, 32(\$s3) add \$t0, \$s2, \$t0 sw \$t0, 32(\$s3) • Remember arithmetic operands are registers, not memory!

11. Compiling using a variable index • Example: g = h + A [i]Assume A is an array of 100 elements whose base is in register \$s3 and that the compiler associates the variables g, h and i with the registers \$s1, \$s2, and \$s4. What is the MIPS assembly code corresponding to this C segment? • Solution:add \$t1, \$s4, \$s4 # Temp reg \$t1 = 2 * iadd \$t1, \$t1, \$t1 # Temp reg \$t1 = 4 *iadd \$t1, \$t1, \$s3 # \$t1 = address of A[i] (4*i+\$s3)lw \$t0, 0(\$t1) # Temporary reg \$t0 = A[i]add \$s1, \$s2, \$t0 # g = h + A[i]

12. Constant and Immediate Operands • The constants would have been placed in memory when the program was loaded. • lw \$t0, AddrConstant4 (\$s1) # \$t0=constant 4add \$s3, \$s3, \$t0 # \$s3=\$s3+\$t0 (\$t0==4) • Assuming that AddrConstant4 is the memory address of the constant 4. • Add immediate (addi) • Addi \$s3, \$s3, 4 #\$s3=\$s3+4 • To add 4 to register \$s3

13. So far we’ve learned: • MIPS — loading words but addressing bytes — arithmetic on registers only • InstructionMeaningadd \$s1, \$s2, \$s3 \$s1 = \$s2 + \$s3sub \$s1, \$s2, \$s3 \$s1 = \$s2 – \$s3lw \$s1, 100(\$s2) \$s1 = Memory[\$s2+100] sw \$s1, 100(\$s2) Memory[\$s2+100] = \$s1

14. Machine Language • Instructions, like registers and words of data, are also 32 bits long • Example: add \$t0, \$s1, \$s2 • registers have numbers, \$t0=8, \$s1=17, \$s2=18 • \$s0~\$s7:16~23, \$t0~\$t7:8-15 • Instruction Format:R-Type0000001000110010 01000 00000 100000 op rs rt rd shamt funct 6 bits 5 bits 5 bits 5bits 5 bits 6 bits

15. Machine Language • MIPS Fields • op: opcode, basic operation of the instruction • rs: the first source operand register • rt: the second source operand register • rd: the destination operand register • shamt: shift amount • funct: function, selects the specific variant of the op

16. Machine Language 6 bits 5 bits 5 bits 16 bits • Consider the load-word and store-word instructions, • What would the regularity principle have us do? • New principle: Good design demands a compromise • Introduce a new type of instruction format • I-type for data transfer instructions • other format was R-type for register • Example:lw \$t0, 32(\$s3)#Temporary reg \$t0 gets A35 19 8 32op rs rt address • Where's the compromise? • To keep all instructions the same length, thereby requiring different kinds of instruction formats for different kinds of instructions. Specifies the destination register

17. MIPS Instruction Encoding

18. Translating MIPS Assembly Language into Machine Language op 0 rs 18 rt 8 rd 8 0 Address/shamt 32 funct 35 9 8 1200 43 9 8 1200 • Example: Assuming that \$t1 has the base of the array A and that \$s2 corresponds to h, the C assignment statementA = h + Ais compiled intolw \$t0, 1200(\$t1)add \$t0, \$s2, \$t0sw \$t0, 1200(\$t1)What is the MIPS machine language code for these three instructions? • Solution:

19. Stored Program Concept Processor Memory • Today’s computers are built on two key principles: • Instructions are represented as numbers (bits) • Programs are stored in memory — to be read or written just like data • Fetch & Execute Cycle • Instructions are fetched and put into a special register • Bits in the register "control" the subsequent actions • Fetch the “next” instruction and continue memory for data, programs, compilers, editors, etc.

20. Instructions for Making Decisions: Control • Decision making instructions • alter the control flow, • i.e., change the "next" instruction to be executed • MIPS conditional branch instructions: • Branch if equal: beqbeq register1, register2, L1if the value of register1equals the value of register2 then go to the statement labeled L1. • Branch if not equal: bnebne register1, register2, L1if the value of register1does not equals the value of register2 then go to the statement labeled L1. • Example: if (i==j) h = i + j;Assume that i, j and h mapping to \$s0,\$s1, and \$s3 bne \$s0, \$s1, Label add \$s3, \$s0, \$s1 Label: ....

21. Example: Compiling an If Statement into a Conditional Branch. • Example: C code segmentif (i == j) go to L1; f = g + h;L1: f = f-i;Assuming that the five variables f through j correspond to the five registers \$s0 through \$s4, what is the compiled MIPS code? • Solution:beq \$s3, \$s4, L1 add \$s0, \$s1, \$s2 L1: sub \$s0, \$s0, \$s3

22. Control: if-then-else • MIPS unconditional branch instructions:j label • Example:if (i!=j) beq \$s3, \$s4, Lab1 h=i+j; add \$s2, \$s3, \$s4 else j Lab2 h=i-j; Lab1: sub \$s2, \$s3, \$s4 Lab2: ... • Example:if ( i == j ) f = g + h; else f = g – h; • Solution:bne \$s3, \$s4, Else add \$s0, \$s1, \$s2 j Exit Else: sub \$s0, \$s1, \$s2 Exit:

23. Control: Loops • Example: Here is a loop in C:Loop: g = g + A[i]; i = i + j; if ( i != h ) goto Loop;Assume that A is in \$s5, g,h, i,j are in \$s1 through \$s4. What is the MIPS assembly code corresponding to this C loop? • Solution:Loop: add \$t1, \$s3, \$s3 #Temp reg \$t1 = 2 * i add \$t1, \$t1, \$t1 #Temp reg \$t1 = 4 * i add \$t1, \$t1, \$s5 #\$t1 = address of A[i] lw \$t0, 0(\$t1) add \$s1, \$s1, \$t0 # g = g + A[i] add \$s3, \$s3, \$s4 # i = i + j bne \$s3, \$s2, Loop # if ( i != h ) goto Loop

24. Control: While Loops • Example: Here is a traditional loop in Cwhile ( save [ i ] == k) i = i + j;Assume that i, j, and k correspond to registers \$s3, \$s4, and \$s5, and the base of the array save is in \$s6. What is the MIPS assembly code corresponding to this C segment? • Solution:Loop: add \$t1, \$s3, \$s3 add \$t1, \$t1, \$t1 add \$t1, \$t1, \$s6 lw \$t0, 0(\$t1)bne \$t0, \$s5, Exit # go to Exit if save[i] != k add \$s3, \$s3, \$s4 # i = i +j j Loop # go to Loop Exit:

25. So far: • InstructionMeaningadd \$s1,\$s2,\$s3 \$s1 = \$s2 + \$s3sub \$s1,\$s2,\$s3 \$s1 = \$s2 – \$s3lw \$s1,100(\$s2) \$s1 = Memory[\$s2+100] sw \$s1,100(\$s2) Memory[\$s2+100] = \$s1bne \$s4,\$s5,L Next instr. is at Label if \$s4 != \$s5beq \$s4,\$s5,L Next instr. is at Label if \$s4 = \$s5j Label Next instr. is at Label • Formats: op rs rt rd shamt funct R I J op rs rt 16 bit address op 26 bit address

26. Control Flow • We have: beq, bne, what about Branch-if-less-than? • New instruction:if \$s1 < \$s2 then \$t0 = 1 slt \$t0, \$s1, \$s2 else \$t0 = 0 • slt (set on less than) • Note that the assembler needs a register to do this, — there are policy of use conventions for registers

27. Control: Branch on Less Than • Example: What is the code to test if register \$s0 is less than register \$s1 and than branch to label Less if the condition holds? • Solution:slt \$t0, \$s0, \$s1 bne \$t0, \$zero, Less • Register \$zero always contains 0. • The pair of instructions,sltand bne, implements branch on less than. • Jump register (jr) • An unconditional jump to the address specified in a register.

28. Control: Case/Switch Statement • The simplest way to implement switch is via a sequence of conditional tests, turning the switch statement into a chain of if-then-else statements. • Encoded as a table of addresses of alternative instruction sequences, called jump address table. • The program needs only to index into the table and then jump to the appropriate sequence. • The jump table is an array of words containing addresses that correspond to labels in the code. • MIPS includes a jump register (jr) instruction, meaning an unconditional jump to the address specified in a register. • The program loads the appropriate entry from the jump table into a register, and then it jumps to the proper address using a jump register.

29. Control: Case/Switch Statement 檢查k是否小於0 檢查k是否小於4 假設JumpTable的起始位址為\$t4 • Example:switch (k) { case 0: f = i + j; break; case 1: f = g + h; break; case 2: f = g - h; break; case 3: f = i - j; break; }Assume that variables f through k correspond to six registers \$s0 through \$s5 and the register \$t2 contains 4. What’s the MIPS code? • Solution:slt \$t3, \$s5, \$zero bne \$t3, \$zero, Exitslt \$t3, \$s5, \$t2 beq \$t3, \$zero, Exit add \$t1, \$s5, \$s5 add \$t1, \$t1, \$t1 add \$t1, \$t1, \$t4 lw \$t0, 0(\$t1) jr \$t0 L0: add \$s0, \$s3, \$s4 j ExitL1: add \$s0, \$s1, \$s2 j Exit L2: sub \$s0, \$s1, \$s2 j Exit L3: sub \$s0, \$s3, \$s4Exit:

30. Control: Case/Switch Statement L0 L1 L2 L3 • Jump address table Jump address table 的起始位址為\$t4，每個location為4 bytes。 Jump Address Table

31. Policy of Use Conventions Register 1 (\$at) reserved for assembler, 26-27 for operating system

32. Supporting Procedures in Computer Hardware • Execution a procedure, the program must follow these six steps: • Place parameters in a place where the procedure can access them • Transfer control to the procedure • Acquire the storage resources need for the procedure. • Perform the desired task. • Place the result value in a place • Return control to the point of origin • MIPS allocates 7 registers for procedure call • \$a0-\$a3: to pass parameters • \$v0-\$v1: to return values • \$ra: to return the point of origin. • Jump-and-link instruction (jal) • jal Procedure Address • The jal instruction saves PC+4 in register \$ra

33. What happens when a procedure is called • Before calling a procedure, the caller must: • 1. Pass the arguments to the callee procedure; • The 4 arguments are passed in registers \$a0-\$a3 (\$4 -\$7). The remaining arguments are placed on the stack. • 2. Save any caller-saved registers that the caller expects to use after the call. This includes the argument registers and the temporary registers \$t0-\$t9. (The callee may use these registers, altering the contents.) • 3. Execute a jal to the called procedure (callee). This saves the return address in \$ra. • At this point, the callee must set up its stack frame: • 1. Allocate memory on the stack by subtracting the frame size from the \$sp. • 2. Save any registers the caller expects to have left unchanged. • These include \$ra, \$fp, and the registers \$s0 - \$s7. • 3. Set the value of the frame pointer by adding the stack frame size to \$fp and subtracting 4. • The procedure can then execute its function. • Note that the argument list on the stack belongs to the stack frame of the caller.

34. Returning from a procedure • When the callee returns to the caller, the following steps are required: • 1. If the procedure is a function returning a value, the value is placed in register \$v0 and, if two words are required, \$v1 (registers \$2 and \$3). • 2. All callee-saved registers are restored by popping the values from the stack, in the reverse order from which they were pushed. • 3. The stack frame is popped by adding the frame size to \$sp. • 4. The callee returns control to the caller by executing jr\$ra • Note that some of the operations may not be required for every procedure call, and modern compilers would only generate the steps required for each particular procedure. • For example, the lowest level subprograms to be called (\leaf nodes") would not have to save \$ra. • If a programming language does not allow a subprogram to call itself (recursion) then implementing a stack frame may not be required, but a stack is still required for nested procedure calls.

35. Supporting Procedures in Computer Hardware (cont.) • Return jump • jr \$ra • Stack (last in first out) • Push: placing data onto the stack • Pop: removing data from the stack • Stack grow from higher address to lower address. • Stack pointer • \$sp : used to save the registers needed by the callee caller callee X (\$a0~\$a3) jalX (\$v0~\$v1) jr \$ra

36. Example: Compiling a procedure that does not call another procedure • What is the compiled MIPS assembly code?int leaf_example(int g, int h, int i, int j){ int f; f = ( g + h ) – ( i + j ); return f;} • SolutionThe parameter variables g, h, i, and j correspond to the argument registers \$a0, \$a1, \$a2, and \$a3, and f corresponds to \$s0.sub \$sp, \$sp, 12sw \$t1, 8(\$sp)sw \$t0, 4(\$sp)sw \$s0, 0(\$sp)add \$t0, \$a0, \$a1add \$t1, \$a2, \$a3sub \$s0, \$t0, \$t1add \$v0, \$s0, \$zerolw \$s0, 0(\$sp)lw \$t0, 4(\$sp)lw \$t1, 8(\$sp)add \$sp, \$sp, 12jr \$ra 在leaf_example的procedure中，會使用到 3個暫時性的暫存器，因此需預留3*4=12byte 將暫存器\$t1, \$t2, \$s0的值，儲存在堆疊中。 將堆疊中的值，回存暫存器\$t1, \$t2, \$s0。

37. Nest Procedures • Push all the other registers that must be preserved onto the stack. • The stack pointer \$sp is adjusted to account for the number of registers placed on the stack.

38. Example: Compiling a recursive procedure, showing nested procedure linking • int fact (int n){ if ( n <1 ) return (1); else return (n * fact (n-1) );} • Solutionfact:sub \$sp, \$sp, 8 sw \$ra, 4(\$sp) sw \$a0, 0(\$sp)slt \$t0, \$a0, 1 #test for n<1 beq \$t0, \$zero, L1 #if n>=1, goto L1 add \$v0, \$zero, 1 #return 1 add \$sp, \$sp, 8 #pop 2 items off stack jr \$ra L1: sub \$a0, \$a0, 1 #n>=1: argument gets (n-1) jal fact #call fact with (n-1)lw \$a0, 0(\$sp) #return from jal: restore argument n lw \$ra, 4 (\$sp) #restore the return address addi \$sp, \$sp, 8 mul \$v0, \$a0, \$v0 jr \$ra 因為會用到\$a0和返回位址\$ra，所以需要2個位址，並且先將\$a0和\$ra儲存在堆疊中。

39. The data segment is divided into 2 parts, the lower part for static data (with size known at compile time) and the upper part, which can grow, upward, for dynamic data structures. The stack segment varies in size during the execution of a program, as functions are called and returned from. It starts at the top of memory and grows down. The MIPS memory allocation for program and data

40. What is preserved across a procedure call

41. Beyond Numbers • Load byte (lb) • Loads a byte from memory, placing it in the rightmost 8 bits of a register. • Store byte (sb) • Takes a byte from the rightmost 8 bits of a register and writes it to memory. • lb \$t0, 0(\$sp) # read byte from sourcesb \$t0, 0(\$sp) # write byte to destination • There are three choices for representing a string: • The first position of the string is reserved to give the length of a string. • An accompanying variable has the length of the string • The last position of a string is indicated by a character used to mark the end of a string.

42. Example: Compiling a string copy procedure, showing how to use C strings • void strcpy (char x[], char y[]){ int i; i = 0; while ( ( x[i] = y[i] ) != 0) i = i + 1 ;} • Solutionstrcpy: sub \$sp, \$sp, 4 #adjust stack for 1 more item sw \$s0, 0(\$sp) # save \$s0 add \$s0, \$zero, \$zero # i = 0L1: add \$t1, \$a1, \$s0 #address of y[i] in \$t1 lb \$t2, 0(\$t1) \$t2 = y[i] add \$t3, \$a0, \$s0 #address of x[i] in \$t3 sb \$t2, 0(\$t3) #x[i] = y[i] beq \$t2, \$zero, L2 # if y[i]==0, go to L2 add \$s0, \$s0, 1 #i = i+1 j L1 # go to L1L2: lw \$s0, 0(\$sp) # y[i] ==0; end of string add \$sp, \$s0, 4 #restore old \$s0, pop 1 word off stack jr \$ra #return array x and y are in \$a0 and \$a1 i is in \$s0

43. Constants op (6 bit) 8 001000 rs (5 bit) 29 11101 rt (5 bit) 29 11101 Immediate(16 bit) 4 0000 0000 0000 0100 • Small constants are used quite frequently (50% of operands) e.g., A = A + 5; B = B + 1; C = C - 18; • Solutions? Why not? • put 'typical constants' in memory and load them. • Ex: to add the constant 4 to register \$spLw \$t0, AddrConstant4add \$sp, \$sp, \$t0 • create hard-wired registers (like \$zero) for constants like one. • Example: Translating Assembly Constants into Machine Language • Solution: addi \$sp, \$sp, 4

44. Immediate Operands 0000 0000 1111 1111 0000 0000 0000 0000 001111 00000 01000 0000 0000 1111 1111 • Immediate version of the set on less than instruction: • slti\$t0, \$s2, 10 #\$t0 = 1 if \$s2 <10 • Load upper immediate instruction: • To set the upper 16 bits of a constant in a register. • lui\$t0, 255 # \$t0 is register 8 The machine language version of lui \$t0, 255 op rs rt immediate Content of register \$t0 after executing lui \$t0, 255

45. How about larger constants? filled with zeros 1010101010101010 0000000000000000 1010101010101010 0000000000000000 0000000000000000 1010101010101010 ori 1010101010101010 1010101010101010 • We'd like to be able to load a 32 bit constant into a register • Must use two instructions, new "load upper immediate" instruction lui \$t0, 1010101010101010 • Then must get the lower order bits right, i.e.,ori \$t0, \$t0, 1010101010101010

46. Example: Loading a 32-bit constant 0000 0000 0011 1101 0000 1001 0000 0000 • What is the MIPS assembly code to load this 32-bit constant into register \$s0?0000 0000 0011 1101 0000 1001 0000 0000 • Solution (1): • lui \$s0, 61addi \$s0, \$s0, 2304 • Solution (2): (discuss in chapter 4) • lui \$s0, 61ori \$s0, \$s0, 2304 0000 0000 0011 1101 0000 0000 0000 0000

47. Addresses in Branches and Jumps op rs rt 16 bit address Conditional branch I J op(6bit) 26 bit address unconditional branch • Instructions: bne \$t4,\$t5,Label Next instruction is at Label if \$t4 <> \$t5 beq \$t4,\$t5,Label Next instruction is at Label if\$t4 = \$t5 j Label Next instruction is at Label • Formats: • Addresses are not 32 bits • How do we handle this with load and store instructions? • Program counter = register + branch address • PC-relative addressing

48. Showing Branch Offset in Machine Language 0 0 0 0 9 19 9 19 9 22 19 20 9 19 9 9 0 0 0 0 32 32 32 32 35 5 8 9 8 21 8 (2) 0 2 80000 (20000) • If we assume that the loop is placed starting at location 80000.Loop: add \$t1, \$s3, \$s3 add \$t1, \$t1, \$t1 add \$t1, \$t1, \$s6 lw \$t0, 0(\$t1) bne \$t0, \$s5, Exit add \$s3, \$s3, \$s4 j Loop Exit: • Solution: 80000 80004 80008 80012 80016 80020 80024 80028

49. Showing Branch Offset in Machine Language (cont.) • The while loop on page 74 was compiled into this MIPS assembler code:Loop: sll \$t1, \$s3, 2 add \$t1, \$t1, \$s6 lw \$t0, 0(\$t1) bne \$t0, \$s5, Exit addi \$s3, \$s3, 1 j LoopExit:If we assume we place the loop starting at location 80000 in memory, what is the MIPS machine code for this loop? 80000 80004 80008 80012 80016 80020

50. Branching Far Away • How about the conditional branch instruction to jump far away? • Insert an unconditional jump to the branch target • Inverts the condition so that the branch decides whether to skip the jump. • Example:Given a branch on register \$s0 being equal to register \$s1beq \$s0, \$s1, L1replace it by a pair of instructions that offers a much greater branching distance. • Solutionbne \$s0, \$s1, L2 j L1L2;