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Instructor: Justin Hsia

CS 61C: Great Ideas in Computer Architecture MIPS CPU Datapath , Control Introduction. Instructor: Justin Hsia. Review of Last Lecture. Critical path constrains clock rate Timing constants: setup, hold, and clk -to-q times Can adjust with extra registers ( pipelining )

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Instructor: Justin Hsia

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  1. CS 61C: Great Ideas in Computer Architecture MIPS CPU Datapath, Control Introduction Instructor: Justin Hsia Summer 2012 -- Lecture #20

  2. Review of Last Lecture • Critical path constrains clock rate • Timing constants: setup, hold, and clk-to-q times • Can adjust with extra registers (pipelining) • Finite State Machines examples of sequential logic circuits • Can implement systems with Register + CL • Use MUXes to select among input • S input bits selects one of 2S inputs • Build n-bit adder out of chained 1-bit adders • Can also do subtraction and overflow detection! Summer 2012 -- Lecture #20

  3. Pipelining Analogy • Santa’s Workshop: elves assemble rocking horses in two parts, each taking ≈ 30 min • Attaching wooden pieces together • Painting • Takes one elf ≈ 60 min • Pass a new set of wood pieces every hour • Split process among two elves in separate rooms (painting is messy) • With added 5 min to transfer from room to room, takes about 65 min to finish one rocking horse • Can pass 1st elf new set of wood pieces every 30 min, 2nd elf finishes a rocking horse every 30 min Summer 2012 -- Lecture #20

  4. lw $t0, 0($2) lw $t1, 4($2) sw $t1, 0($2) sw $t0, 4($2) Great Idea #1: Levels of Representation/Interpretation temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; Higher-Level LanguageProgram (e.g. C) Compiler Assembly Language Program (e.g. MIPS) Assembler 0000 1001 1100 0110 1010 1111 0101 1000 1010 1111 0101 1000 0000 1001 1100 0110 1100 0110 1010 1111 0101 1000 0000 1001 0101 1000 0000 1001 1100 0110 1010 1111 Machine Language Program (MIPS) We are here Machine Interpretation Hardware Architecture Description(e.g. block diagrams) Architecture Implementation Logic Circuit Description(Circuit Schematic Diagrams) Summer 2012 -- Lecture #20

  5. Hardware Design Hierarchy system control datapath coderegisters stateregisters combinationallogic multiplexer comparator register logic Today switchingnetworks Summer 2012 -- Lecture #20

  6. Agenda • Processor Design • Administrivia • Datapath Overview • Assembling the Datapath • Control Introduction Summer 2012 -- Lecture #20

  7. Five Components of a Computer • Components a computer needs to work • Control • Datapath • Memory • Input • Output Computer Processor Memory Devices Control (“brain”) Input Datapath (“brawn”) Output Summer 2012 -- Lecture #20

  8. The Processor • Processor (CPU): Implements the instructions of the Instruction Set Architecture (ISA) • Datapath: part of the processor that contains the hardware necessary to perform operations required by the processor (“the brawn”) • Control: part of the processor (also in hardware) which tells the datapath what needs to be done (“the brain”) Summer 2012 -- Lecture #20

  9. Processor Design Process • Five steps to design a processor: 1. Analyze instruction set datapath requirements 2. Select set of datapathcomponents & establish clock methodology 3. Assemble datapath meeting the requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer 5. Assemble the control logic • Formulate Logic Equations • Design Circuits Now Processor Input Control Memory Datapath Output Summer 2012 -- Lecture #20

  10. 31 26 21 16 11 6 0 op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits The MIPS-lite Instruction Subset • ADDU and SUBU • addurd,rs,rt • suburd,rs,rt • OR Immediate: • ori rt,rs,imm16 • LOAD and STORE Word • lw rt,rs,imm16 • sw rt,rs,imm16 • BRANCH: • beq rs,rt,imm16 Summer 2012 -- Lecture #20

  11. Register Transfer Language (RTL) • All start by fetching the instruction: • RTL gives the meaning of the instructions: R-format: {op, rs, rt, rd, shamt, funct}  MEM[ PC ] I-format: {op, rs, rt, imm16}  MEM[ PC ] Inst Register Transfers ADDU R[rd]R[rs]+R[rt]; PCPC+4 SUBU R[rd]R[rs]–R[rt]; PCPC+4 ORI R[rt]R[rs]|zero_ext(imm16); PCPC+4 LOAD R[rt]MEM[R[rs]+sign_ext(imm16)]; PCPC+4 STORE MEM[R[rs]+sign_ext(imm16)]R[rt]; PCPC+4 BEQ if ( R[rs] == R[rt] ) then PCPC+4 + (sign_ext(imm16) || 00) else PCPC+4 Summer 2012 -- Lecture #20

  12. Step 1: Requirements of the Instruction Set • Memory (MEM) • Instructions & data (separate: in reality just caches) • Load from and store to • Registers (32 32-bit regs) • Read rs and rt • Write rtor rd • PC • Add 4 (+ maybe extended immediate) • Extender (sign/zero extend) • Add/Sub/OR unit for operation on register(s) or extended immediate • Compare if registers equal? Summer 2012 -- Lecture #20

  13. ALU 1. Instruction Fetch 4. Memory 5. Register Write 2. Decode/ Register Read 3. Execute Generic Datapath Layout • Break up the process of “executing an instruction” • Smaller phases easier to design and modify independently • Proj1 had 3 phases: Fetch, Decode, Execute • Now expand Execute Register File rd instruction memory PC rs Data memory rt +4 imm MUX Summer 2012 -- Lecture #20

  14. Adder ALU Step 2: Components of the Datapath CarryIn A • Combinational Elements • Gates and wires • State Elements + Clock • Building Blocks: 32 Sum 32 B CarryOut 32 Select A 32 MUX Y 32 B 32 OP Adder ALU A Multiplexer 32 Result 32 B 32 Summer 2012 -- Lecture #20

  15. ALU Requirements • MIPS-lite: add, sub, OR, equality ADDU R[rd] = R[rs] + R[rt]; ... SUBU R[rd] = R[rs] – R[rt]; ... ORI R[rt] = R[rs] | zero_ext(Imm16)... BEQ if ( R[rs] == R[rt] )... • Equality test: Use subtraction and implement output to indicate if result is 0 • P&H also adds AND, Set Less Than (1 if A < B, 0 otherwise) • Can see ALU from P&H C.5 (on CD) Summer 2012 -- Lecture #20

  16. Storage Element: Idealized Memory Write Enable Address • Memory (idealized) • One input bus: Data In • One output bus: Data Out • Memory access: • Read: Write Enable = 0, data at Address is placed on Data Out • Write: Write Enable = 1, Data In written to Address • Clock input (CLK) • CLK input is a factor ONLY during write operation • During read, behaves as a combinational logic block: Address valid Data Out valid after “access time” Data In DataOut 32 32 CLK Summer 2012 -- Lecture #20

  17. Write Enable Data In Data Out N N CLK Storage Element: Register • As seen in Logisim intro • N-bit input and output buses • Write Enable input • Write Enable: • De-asserted (0): Data Out will not change • Asserted (1): Data In value placed onto Data Out on the rising edge of CLK Summer 2012 -- Lecture #20

  18. Storage Element: Register File RW RA RB Write Enable 5 5 5 • Register File consists of 32 registers: • Output buses busA and busB • Input bus busW • Register selection • Place data of register RA (number) onto busA • Place data of register RB(number) onto busB • Store data on busWinto register RW (number) when Write Enable is 1 • Clock input (CLK) • CLK input is a factor ONLY during write operation • During read, behaves as a combinational logic block:RA or RB valid busA or busB valid after “access time” busA busW 32 32 x 32-bit Registers 32 busB Clk 32 Summer 2012 -- Lecture #20

  19. Agenda • Processor Design • Administrivia • Datapath Overview • Assembling the Datapath • Control Introduction Summer 2012 -- Lecture #20

  20. Administrivia • HW 4 due Wednesday • Project 2, Part 2 due Sunday 7/29 • Extra Credit also due 7/29 (Fastest Matrix Multiply) • No lab on Thursday – work on project Summer 2012 -- Lecture #20

  21. Agenda • Processor Design • Administrivia • Datapath Overview • Assembling the Datapath • Control Introduction • Clocking Methodology Summer 2012 -- Lecture #20

  22. ALU 1. Instruction Fetch 4. Memory 5. Register Write 2. Decode/ Register Read 3. Execute Datapath Overview (1/5) • Phase 1: Instruction Fetch (IF) • Fetch 32-bit instruction from memory • Increment PC (PC = PC + 4) Register File rd instruction memory PC rs Data memory rt +4 imm MUX Summer 2012 -- Lecture #20

  23. ALU 1. Instruction Fetch 4. Memory 5. Register Write 2. Decode/ Register Read 3. Execute Datapath Overview (2/5) • Phase 2: Instruction Decode (ID) • Read the opcode and appropriate fields from the instruction • Gather all necessary registers values from Register File Register File rd instruction memory PC rs Data memory rt +4 imm MUX Summer 2012 -- Lecture #20

  24. ALU 1. Instruction Fetch 4. Memory 5. Register Write 2. Decode/ Register Read 3. Execute Datapath Overview (3/5) • Phase 3: Execute (EX) • ALU performs operations: arithmetic (+,-,*,/), shifting, logical (&,|), comparisons (slt,==) • Also calculates addresses for loads and stores Register File rd instruction memory PC rs Data memory rt +4 imm MUX Summer 2012 -- Lecture #20

  25. ALU 1. Instruction Fetch 4. Memory 5. Register Write 2. Decode/ Register Read 3. Execute Datapath Overview (4/5) • Phase 4: Memory Access (MEM) • Only load and store instructions do anything during this phase; the others remain idle or skip this phase • Should be fast due to caches Register File rd instruction memory PC rs Data memory rt +4 imm MUX Summer 2012 -- Lecture #20

  26. ALU 1. Instruction Fetch 4. Memory 5. Register Write 2. Decode/ Register Read 3. Execute Datapath Overview (5/5) • Phase 5: Register Write (WB for “write back”) • Write the instruction result back into the Register File • Those that don’t (e.g. sw, j, beq) remain idle or skip this phase Register File rd instruction memory PC rs Data memory rt +4 imm MUX Summer 2012 -- Lecture #20

  27. Why Five Stages? • Could we have a different number of stages? • Yes, and other architectures do • So why does MIPS have five if instructions tend to idle for at least one stage? • The five stages are the union of all the operations needed by all the instructions • There is one instruction that uses all five stages: load (lw/lb) Summer 2012 -- Lecture #20

  28. Agenda • Processor Design • Administrivia • Datapath Overview • Assembling the Datapath • Control Introduction Summer 2012 -- Lecture #20

  29. Step 3: Assembling the Datapath • Assemble datapath to meet RTL requirements • Exact requirements will change based on ISA • Here we will examine each instruction of MIPS-lite • The datapath is all of the hardware components and wiring necessary to carry out all of the different instructions • Make sure all components (e.g. RegFile, ALU) have access to all necessary signals and buses • Control will make sure instructions are properly executed (the decision making) Summer 2012 -- Lecture #20

  30. Next Address Logic Address Instruction Memory Datapath by Instruction • All instructions: Instruction Fetch (IF) • Fetch the Instruction: mem[PC] • Update the program counter: • Sequential Code:PC  PC + 4 • Branch and Jump: PC  “something else” CLK PC Instruction 32 Summer 2012 -- Lecture #20

  31. Datapath by Instruction • All instructions: Instruction Decode (ID) • Pull off all relevant fields from instruction to make available to other parts of datapath • MIPS-lite only has R-format and I-format • Control will sort out the proper routing (discussed later) opcode Wires and Splitters rs rt Instr rd 16 32 6 5 5 5 5 6 shamt funct imm Summer 2012 -- Lecture #20

  32. Step 3: Add & Subtract • ADDU R[rd]R[rs]+R[rt]; • Hardware needed: • Instruction Mem and PC (already shown) • Register File (RegFile) for read and write • ALU for add/subtract 5 5 5 busA A RW RA RB busW 32 32 Result 32 x 32-bit Registers ALU 32 busB B 32 CLK 32 32 Summer 2012 -- Lecture #20

  33. Step 3: Add & Subtract • ADDU R[rd]R[rs]+R[rt]; • Connections: • RegFile and ALU Inputs • Connect RegFile and ALU • RegWr (1) and ALUctr (ADD/SUB) set by control in ID rd rs rt ALUctr RegWr 5 5 5 busA A RW RA RB busW 32 32 Result 32 x 32-bit Registers ALU 32 busB B 32 CLK 32 32 Summer 2012 -- Lecture #20

  34. Step 3: Or Immediate • ORI R[rt]R[rs]|zero_ext(Imm16); • Is the hardware below sufficient? • Zero extend imm16? • Pass imm16 to input of ALU? • Write result to rt? rd rs rt ALUctr RegWr 5 5 5 busA RW RA RB busW 32 Result 32 x 32-bit Registers ALU 32 busB 32 CLK 32 Summer 2012 -- Lecture #20

  35. ALU Step 3: Or Immediate • ORI R[rt]R[rs]|zero_ext(Imm16); • Add new hardware: • Still support add/sub • New control signals:RegDst, ALUSrc RegDst rd rt 2:1 MUX 1 0 RegWr rs rt ALUctr 5 5 5 busA 32 RW RA RB 32 RegFile busB 32 0 32 CLK imm16 1 ZeroExt 16 32 ALUSrc How to implement this? Summer 2012 -- Lecture #20

  36. ALU Step 3: Load • LOAD R[rt]MEM[R[rs]+sign_ext(Imm16)]; • Hardware sufficient? • Sign extend imm16? • Where’s MEM? RegDst rd rt 1 0 RegWr rs rt ALUctr 5 5 5 busA 32 RW RA RB 32 RegFile busB 32 0 32 CLK imm16 1 ZeroExt 16 32 ALUSrc Summer 2012 -- Lecture #20

  37. 1 0 ALU 0 1 Step 3: Load • LOAD R[rt]MEM[R[rs]+sign_ext(Imm16)]; • New control signals: ExtOp, MemWr, MemtoReg ALUctr RegDst rd rt MemtoReg MemWr What goes here during a store? RegWr rs rt 5 5 5 busA 32 RW RA RB busW 32 RegFile busB 32 0 32 CLK 32 WrEn Addr ??? Must nowalso handlesign extension imm16 Data In 1 Extender Data Memory 16 32 CLK ALUSrc ExtOp Summer 2012 -- Lecture #20

  38. 1 0 ALU 0 1 Step 3: Store • STORE MEM[R[rs]+sign_ext(Imm16)]R[rt]; • Connect busB to DataIn (no extra control needed!) ALUctr RegDst rd rt MemtoReg MemWr RegWr rs rt 5 5 5 busA 32 RW RA RB busW 32 RegFile busB 32 0 32 CLK 32 WrEn Addr imm16 Data In 1 Extender Data Memory 16 32 CLK ALUSrc ExtOp Summer 2012 -- Lecture #20

  39. 1 0 ALU 0 1 Step 3: Branch If Equal • BEQ if(R[rs]==R[rt]) then PCPC+4 + (sign_ext(Imm16) || 00) • Need comparison output from ALU ALUctr RegDst rd rt MemtoReg MemWr zero RegWr rs rt 5 5 5 busA 32 RW RA RB = busW 32 RegFile busB 32 0 32 CLK 32 WrEn Addr imm16 Data In 1 Extender Data Memory 16 32 CLK ALUSrc ExtOp Summer 2012 -- Lecture #20

  40. Next Address Logic Address Addr Instruction Memory Instruction Memory Step 3: Branch If Equal • BEQ if(R[rs]==R[rt]) then PCPC+4 + (sign_ext(Imm16) || 00) • Revisit “next address logic”: How to hook these up? nPC_sel zero ??? 4 Instruction Adder CLK PC 0 32 Sign extendand ×4 MUX PC 1 Adder Instruction PC Ext CLK 32 imm16 Instr Fetch Unit Summer 2012 -- Lecture #20

  41. Step 3: Branch If Equal • BEQ if(R[rs]==R[rt]) then PCPC+4 + (sign_ext(Imm16) || 00) • Revisit “next address logic”: • nPC_sel should be 1 if branch, 0 otherwise nPC_sel zero MUX PC+4 0 nextPC (nPC) MUX 1 PC+4 + branchAddr How does this changeif we add bne? Summer 2012 -- Lecture #20

  42. Addr Instruction Memory Step 3: Branch If Equal • BEQ if(R[rs]==R[rt]) then PCPC+4 + (sign_ext(Imm16) || 00) • Revisit “next address logic”: nPC_sel zero 4 Instruction Adder 0 32 MUX PC 1 Adder PC Ext CLK imm16 Instr Fetch Unit Summer 2012 -- Lecture #20

  43. Get To Know Your Staff • Category: Movies Summer 2012 -- Lecture #20

  44. Agenda • Processor Design • Administrivia • Datapath Overview • Assembling the Datapath • Control Introduction Summer 2012 -- Lecture #20

  45. Processor Design Process • Five steps to design a processor: 1. Analyze instruction set datapath requirements 2. Select set of datapathcomponents & establish clock methodology 3. Assemble datapath meeting the requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer 5. Assemble the control logic • Formulate Logic Equations • Design Circuits Processor Now Input Control Memory Datapath Output Summer 2012 -- Lecture #20

  46. Control • Need to make sure that correct parts of the datapath are being used for each instruction • Have seen control signalsin datapath used to select inputs and operations • For now, focus on what value each control signal should be for each instruction in the ISA • Next lecture, we will see how to implement the proper combinational logic to implement the control Summer 2012 -- Lecture #20

  47. 1 1 0 0 ALU ALU 0 0 1 1 Desired Datapath For addu • R[rd]R[rs]+R[rt]; Instruction <31:0> Instruction <31:0> nPC_sel=? nPC_sel=? nPC_sel=? Instr Fetch Unit Instr Fetch Unit +4 <0:15> <0:15> <21:25> <21:25> <16:20> <16:20> <11:15> <11:15> CLK CLK RegDst=? RegDst=? RegDst=? rd rd rt rt 1 rs rs rt rt rd rd imm16 imm16 ALUctr=? ALUctr=? ALUctr=? ADD RegWr=? RegWr=? rs rs rt rt RegWr=? 1 zero zero 5 5 5 5 5 5 MemtoReg=? MemtoReg=? MemtoReg=? 0 MemWr=? busA busA 32 32 MemWr=? MemWr=? 0 RW RW RA RA RB RB RegFile RegFile = = busW busW 32 32 busB busB 32 32 0 0 32 32 CLK CLK 32 32 WrEn WrEn Addr Addr Data Memory Data Memory imm16 imm16 Data In Data In 1 1 Extender Extender 16 16 32 32 CLK CLK ALUSrc=? ALUSrc=? ALUSrc=? 0 ExtOp=? ExtOp=? ExtOp=? X Summer 2012 -- Lecture #20

  48. 1 1 0 0 ALU ALU 0 0 1 1 Desired Datapath For ori • R[rt]R[rs]|ZeroExt(imm16); Instruction <31:0> Instruction <31:0> nPC_sel=? nPC_sel=? Instr Fetch Unit Instr Fetch Unit +4 <0:15> <0:15> <21:25> <21:25> <16:20> <16:20> <11:15> <11:15> CLK CLK RegDst=? RegDst=? rd rd rt rt 0 rs rs rt rt rd rd imm16 imm16 ALUctr=? ALUctr=? OR RegWr=? RegWr=? rs rs rt rt 1 zero zero 5 5 5 5 5 5 MemtoReg=? MemtoReg=? 0 busA busA 32 32 MemWr=? MemWr=? 0 RW RW RA RA RB RB RegFile RegFile = = busW busW 32 32 busB busB 32 32 0 0 32 32 CLK CLK 32 32 WrEn WrEn Addr Addr Data Memory Data Memory imm16 imm16 Data In Data In 1 1 Extender Extender 16 16 32 32 CLK CLK ALUSrc=? ALUSrc=? 1 ExtOp=? ExtOp=? Zero Summer 2012 -- Lecture #20

  49. 1 1 0 0 ALU ALU 0 0 1 1 Desired Datapath For load • R[rt]MEM{R[rs]+SignExt[imm16]}; Instruction <31:0> Instruction <31:0> nPC_sel=? nPC_sel=? Instr Fetch Unit Instr Fetch Unit +4 <0:15> <0:15> <21:25> <21:25> <16:20> <16:20> <11:15> <11:15> CLK CLK RegDst=? RegDst=? rd rd rt rt 0 rs rs rt rt rd rd imm16 imm16 ALUctr=? ALUctr=? ADD RegWr=? RegWr=? rs rs rt rt 1 zero zero 5 5 5 5 5 5 MemtoReg=? MemtoReg=? 1 busA busA 32 32 MemWr=? MemWr=? 0 RW RW RA RA RB RB RegFile RegFile = = busW busW 32 32 busB busB 32 32 0 0 32 32 CLK CLK 32 32 WrEn WrEn Addr Addr Data Memory Data Memory imm16 imm16 Data In Data In 1 1 Extender Extender 16 16 32 32 CLK CLK ALUSrc=? ALUSrc=? 1 ExtOp=? ExtOp=? Sign Summer 2012 -- Lecture #20

  50. 1 1 0 0 ALU ALU 0 0 1 1 Desired Datapath For store • MEM{R[rs]+SignExt[imm16]}R[rt]; Instruction <31:0> Instruction <31:0> nPC_sel=? nPC_sel=? Instr Fetch Unit Instr Fetch Unit +4 <0:15> <0:15> <21:25> <21:25> <16:20> <16:20> <11:15> <11:15> CLK CLK RegDst=? RegDst=? rd rd rt rt X rs rs rt rt rd rd imm16 imm16 ALUctr=? ALUctr=? ADD RegWr=? RegWr=? rs rs rt rt 0 zero zero 5 5 5 5 5 5 MemtoReg=? MemtoReg=? X busA busA 32 32 MemWr=? MemWr=? 1 RW RW RA RA RB RB RegFile RegFile = = busW busW 32 32 busB busB 32 32 0 0 32 32 CLK CLK 32 32 WrEn WrEn Addr Addr Data Memory Data Memory imm16 imm16 Data In Data In 1 1 Extender Extender 16 16 32 32 CLK CLK ALUSrc=? ALUSrc=? 1 ExtOp=? ExtOp=? Sign Summer 2012 -- Lecture #20

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