Adaptive Data Analysis and Processing Technology (ADAPT)

1. Adaptive Data Analysis and Processing Technology (ADAPT) Carl Mills, Glenn Hines, and Steve Jurczyk NASA Langley Research Center, Langley VA Ann Garrison Darrin, Richard Conde, Harry Eaton Bobbie Chern (intern) - The Johns Hopkins University Applied Physics Laboratory Phil Luers, NASA Goddard Space Flight Center, Greenbelt, MD

2. Team Members NASA GSFC Phil Luers Philip.J.Luers.1@gsfc.nasa.gov 301-286-5777 NASA LaRC Steve Jurczyk S.G.Jurczyk@larc.nasa.gov Carl Mills C.S.Mills@larc.nasa.gov The Johns Hopkins University Applied Physics Laboratory Rich Conde Rich.Conde@jhuapl.edu 240-228-8876 Ann Garrison Darrin Ann.Darrin@jhuapl.edu 240-228-4952 Queensland University of Technology High Performance Computing Center Dr. Neil Bergmann, QUT Dr. Anwar Dawood, QUT a.dawood@qut.edu.au

3. Reconfigurable Computers Especially for Spacecraft Use • Adapt to changing mission requirements, even after launch • Decrease spacecraft onboard storage and downlink resources needed by high data instruments by reducing instrument data rates in the instrument • Allow hardware fabrication before algorithms are completed • Allow algorithms to be updated or corrected after launch • Reduce engineering set up times for science observatories

4. Drivers for Using SRAM Based Technology • Engineering setup times for science observations greatly reduced • FPGAs offer high performance and good capability in terms of processing power per chip • Physical design remains the same: control and data interfaces can be easily tailored • Minimizes instrument or system development time • In Flight configuration to mitigate hardware and software errors • Multiple configurations can be stored for rapid adaptations

5. ESE Technology Challenges Addressed by Reconfigurable Computing • Atmospheric Composition and Ozone • Visible (VIS), near-infrared (NIR), and short-wave infrared (SWIR) spectrometers for stratospheric chemistry research • Infrared (IR) spectrometers including Fourier Transform Spectrometers (FTS), and UV and SWIR imaging radiometers/spectrometers for tropospheric chemistry research • Ultra-violet (UV) and VIS/NIR/SWIR spectrometers, and VIS-SWIR radiometers to measure aerosol properties • Climate Variability and Change • Lidar and radar altimeters, radar interferometers, radiometers, and GPS receivers for ocean surface topography • Global Carbon Cycle • Vis-SWIR radiometers for land cover and land use change research • Global Water and Energy Cycle • VIS/NIR/SWIR and IR spectrometers atmospheric temperature and humidity measurements • Microwave radiometers for soil moisture measurements • Microwave spectrometers/scatterometers for cloud property measurements • VIS-SWIR radiometers for cold hydrologic process studies • Solid Earth and Natural Hazards • Vis-SWIR radiometers for lightning mapping • UV and Vis-SWIR radiometers for volcanic ash cloud measurements

6. 1st Demonstration of Reconfigurable Computer Using SRAM based Technology in Space • FedSat-1 is a 50 kg microsatellite in a Low Earth orbit of ~1000 km altitude. • Adaptive Instrument Module (AIM) (Precursor to ADAPT) • The AIM demonstrates the first reconfigurable computer being developed at APL • It is a standalone unit that includes an 80C196 general purpose processor and a Xilinx XQR4062 FPGA that performs reconfigurable processing • It weighs 890 grams and dissipates under 2.W • It is scheduled to fly on the Australian FEDSAT spacecraft in Spring 2002 • AIM partners include APL, Queensland University of Technology, Goddard Spaceflight Center, and Langley Research Center

7. AIM Flight Unit Test

8. ADAPT - Hardware Definition • ADAPT stores multiple FPGA configurations in flash memory. • Host processor selects which configuration to use. • Instrument data processing algorithms can be changed in real time. • Fuse-programmed Actel FPGA implements the system interface that the host processor uses to choose the Xilinx Virtex II FPGA configurations. • Second Actel FPGA performs read back and verification of the Xilinx FPGA’s configuration. • If discrepancies are detected, the configuration is automatically corrected and the host processor is notified of the upset. • Instrument data may flow through the PCI bus or an I/O connector.

9. ADAPT - Hardware Definition • The ADAPT includes voltage regulators to supply the low-voltage needs of on-board components. • The backplane need only supply standard +3.3V, +5V power. • Xilinx FPGA clock can be supplied by the on-board oscillator, the PCI bus clock, or from the I/O connector. • Xilinx FPGA on-chip temperature sensor is routed to I/O connector.

10. ADAPT Hardware Designbased on widespread commercial standards • The ADAPT implements complex algorithms directly in reconfigurable hardware for processing of high rate instrument data. • Utilizes state of the art Xilinx Virtex II FPGA (Contains the equivalent of 1 million gates and 720k bits of RAM. • A wide range of IP cores are available: • DSP functions • Processors • Math functions. • New designs can be implemented with a wide range of development tools. • In ADAPT design, the Xilinx FPGA is connected to external SRAM memory to implement additional storage for intermediate results, coefficients, and variables that some algorithms may require.

11. Voltage Regulators PCI Bus Power SRAM Oscillator Front Panel I/O Connector (Instrument Data) J2 I/O Connector on back-plane (Instrument Data) Xilinx Virtex II FPGA (XC2V1000) Actel Supervisor (Configuration/Readback) Flash Memory Actel Host interface ADAPT Board Block Diagram PCI Bus (Host Processor Communications)

12. Accomplishments to Date • Hardware design completed • Developed a simplified technique for partial-reconfiguration (SEU correction) • Efficient format for storing configuration/readback data in flash memory developed (3 times reduction in memory over standard bitstream format) • Software that converts Xilinx bitstream files to ADAPT format begun • Completed design/assembly/test of test-adapter board that allows software driven testing of Xilinx configuration interface (no models are available from Xilinx) • Layout of ADAPT board complete, presently in fabrication • All components ready for assembly

13. Project Schedule

14. Upcoming Activities • ADAPT board assembly • Supervisor state-machine test using test-board. • Simulation of SEU in Xilinx FPGA • Design/programming of Actel FPGAs • Host processor software development • System level testing

15. Example of Instrument Using ADAPT • ADAPT implements realtime data reduction, data compression, and feature extraction algorithms. This minimizes the use of spacecraft resources such as onboard data storage and downlink bandwidth • Since it is generic, the same design can be used for different instruments Instrument Sensor Front End Electronics 3U Compact PCI Backplane ADAPT Instrument Processor Spacecraft C&DH Interface Spacecraft Interface Spacecraft Power DC/DC Converters

16. Drivers for Using SRAM Based Technology • Engineering setup times for science observations greatly reduced • FPGAs offers extremely dense performance in terms of capability processing chip • Physical design remains the same: control and data interfaces can be easily tailored • Minimum instrument or system development time • In Flight configuration to mitigate hardware and software errors • Multiple FPGAs provide a scaleable architecture • Multiple configurations can be stored for rapid adaptations

17. FedSat • FedSat-1 is a microsatellite • 50 kg mass • Low Earth orbit ~1000 km altitude. • The 5 principle missions of FedSat: • communications • space science • remote sensing • engineering research • education/training

18. Reconfigurability Experiments • Proof of Concept Experiment • Standard generic interface • Reconfiguration • Uploading Information • Error Correction (effects of radiation)

19. AIM Adaptive Instrument Module ADAPT Adaptive Processing Template C3PO Configurable 3U Compact PCI

20. Adaptive Instrument Module (AIM) • The AIM demonstrates the first reconfigurable computer being developed at APL • It is a standalone unit that includes an 80C196 general purpose processor and a Xilinx XQR4062 FPGA that performs reconfigurable processing • It weighs 890 grams and dissipates under 2.W • It is scheduled to fly on the Australian FEDSAT spacecraft in Spring 2002 • AIM partners include APL, Queensland University of Technology, Goddard Spaceflight Center, and Langley Research Center

21. AIM Block Diagram Spacecraft C&DH Interface 80C196 Microprocessor 8 MByte Flash Memory (Configurations) 256 KByte EEPROM Memory (Boot Code) 512 KByte SRAM Memory (Code/Data) Data Bus +28V Spacecraft Power +5V Power Regulation Memory Controller Readback Circuitry +3.3V Configuration Expanded Address Bus Instrument Control or Spacecraft Reconfigurable Computing Unit Xilinx XQR4062 Instrument/Sensor Output 8 KByte SRAM

22. Sample Experiments for the AIM on FEDSAT in Flight: • Real Time Image Processing on Board Satellite Systems • Real time image processing on board satellite systems for disaster prediction and early warning mechanism. Images gathered by on board video cameras can be processed on board the satellite and compared with normal status images stored on a database system. Identification of changes will cause sending early warning messages to ground. The project aims at implementing search algorithms and matching algorithms on reconfigurable computing technology for higher performance • Prototype System for Image Processing on Reconfigurable Computing Technology • Investigates the development of a prototype system for efficient image processing using custom computing to achieve high performance. Image processing algorithms such as search algorithms, matching algorithms and other image processing techniques such image filtering and compression will be investigated and implemented on reconfigurable computing technology platform utilising the capacity of FPGAs for better performance. • Image Compression and Filtering Techniques on Board Satellite Systems • This project explores image compression and filtering algorithms and potential improvement by implementation on reconfigurable computing technology for on board image processing of satellite systems. The project aims to develop improved compression and filtering techniques. The new algorithms are to be implemented and tested on FPGAs platform for higher performance.

23. ADAPT • ADAPT stores multiple FPGA configurations in flash memory. • Host processor selects which configurations are to be used. • Instrument data processing algorithms changed in realtime. • Fuse-programmed Actel FPGA implements the system interface to allow the system host processor to select the configurations to be loaded into the Virtex FPGAs. • Second Actel includes the circuitry to read back the configuration from the Xilinx FPGAs and compare it to the original configuration in flash memory. • If discrepancies are detected, the configuration is autonomously reloaded, and the host processor is notified that data processing will be halted for a few seconds. • Instrument data may be inputted either through the PCI bus or an I/O connector.

24. ADAPT • The ADAPT includes a voltage regulator to supply power to the Virtex FPGAs. • The voltage regulator is kept on the ADAPT board so that the host system will not have to generate +2.5V. • It is expected that the card will only need to be supplied with +3.3V from the backplane. • An oscillator supplies the clock needed to run the Actel FPGAs. The temperature of the Virtex parts and the linear regulator will be measured by thermistors. The thermistors will be connected to an I/O connector.

25. ADAPT Board Block Diagram3U Compact PCI

26. Instrument Sensor Front End Electronics 3U Compact PCI Backplane ADAPT Instrument Processor Spacecraft C&DH Interface Spacecraft Interface Spacecraft Power DC/DC Converters Example of Instrument Using ADAPT • ADAPT implement realtime data reduction, data compression, and feature extraction algorithms. This minimizes the use of spacecraft resources such as onboard data storage and downlink bandwidth • Since it is generic, the same design can be used for different instruments

27. Spacecraft Architecture with ADAPT • An instrument that uses the ADAPT card can either have its own Compact PCI chassis, or it could be integrated directly into the spacecraft Compact PCI chassis. • The second approach would yield a lower mass system, since the digital electronics for the instrument (the ADAPT card) could exist as an additional card in the spacecraft chassis, rather than as a stand alone chassis. • Since the bulk of the instrument processing is done in the ADAPT card, the spacecraft processor card can do the remainder of the processing with a small percentage of its resources, for example packetizing the reduced science data or transferring the packets to the spacecraft solid state recorder. • If the extra mass is available, a separate Instrument Compact PCI chassis with a dedicated processor could be implemented.

28. Technology Description and Benefits • In the past, system flexibility was primarily associated with system software. • New functions and applications were accomplished by changing the sequence of instructions executed by a general-purpose processor. • The next step forward is to make the hardware itself adaptable and the ADAPT pursues this challenge by developing a reconfigurable processor board that will be capable of functioning efficiently in various applications. • ADAPT will take advantage of radiation tolerant RAM-based field programmable gate array (FPGA) technology to develop a reconfigurable processor that combines the flexibility of a general purpose processor running software with the performance of application specific processing hardware for a variety of high performance computing applications.

29. Hardware Concepts Requirements and Efficiency Metrics • Power and Mass efficiency of the C3PO: • Compact 3U PCI footprint is 481mm x 177mm x 195mm (19.0" x 7.0" x 7.7") with a total weight of < 230 grams • Size and density of the network file system -The resources of the Xilinx FPGA (1.1 million gate, 131,000 RAM bits, up to 200 MHz performance) allows implementation of immediate processing of sensor data into science data products. • Complex functions such as a 1024 point FFT processor purchased at low cost instead of developing them from scratch. This processing of image and signal data in the instrument greatly reduces the required data storage and downlink bandwidth. • C3P0 Radiation dose tolerance greater than 30 Krad (Si) – Virtex family of Radiation hardened parts are specified to greater that 100Krad (SI) and latch up immune. • No more than one single event upset induced error per year without detection and correction as appropriate • High reliability EEE Parts