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ITk RD Fase2@ATLAS C . Gemme – INFN Genova On behalf of ATLAS RD_FASE2 PIXEL:

ITk RD Fase2@ATLAS C . Gemme – INFN Genova On behalf of ATLAS RD_FASE2 PIXEL: BO , CS, GE, LE, MI, TIFPA, UD Incontro con i referee - 9 Giugno 2016. Outline. ITk Layout TF e Strip/Pixel timeline Overview del coinvolgimento INFN in RD-Fase2 Aggiornamenti Elettronica **

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ITk RD Fase2@ATLAS C . Gemme – INFN Genova On behalf of ATLAS RD_FASE2 PIXEL:

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  1. ITk RD Fase2@ATLAS C. Gemme – INFN Genova On behalf of ATLAS RD_FASE2 PIXEL: BO, CS, GE, LE, MI, TIFPA, UD Incontro con i referee - 9 Giugno 2016

  2. Outline • ITk Layout TF e Strip/Pixel timeline • Overview del coinvolgimento INFN in RD-Fase2 • Aggiornamenti • Elettronica** • Sensori 3D (comuni a CMS) • Ibridizzazione: bump-bonding e accoppiamentocapacitivo • Cooling • Simulazioni

  3. ITK Layout: Step program Final ITk layout is still under study driven by a Task Force. Big modifications since the Letter of Intent. • STEP 1.0: Done! • 5P+4S (LoI was 4P + 5.1S) • Four different pixel layouts (extended & inclined) and eta coverage • A close to final strip barrel and end-cap • Some single particle studies …. Mainly tests of procedures used throughout the process • STEP 1.5: on-going • To be used for the Strip TDR and ECFA studies • Needs to be able to run in ATLAS sw with sFCal and NSW • Includes tracking and physics performance • Goals • Same layouts as Step 1.0 but … • Improved materials description including details of services • Realistic strip end-cap description (petals, not modules) • Used to iterate ring layout – where we anticipate a reduction in the number of hits • STEP 2.0 • Iteration of layouts towards new baseline and Pixel TDR • To be used for final TF recommendation (EoY)

  4. ITK Layouts (1.0 and 1.5) Strip layout and Pixel end-cap all the same. Changes only in the Pixel barrel.

  5. Pixel production Schedule • The start time of mass module production is determined by the availability of the FE chip (developed through RD53 and ATLAS). • The current schedule indicates that the pre-production will run from mid-2019 and the start of the bulk production by mid-2020. • About the end-date, it seems reasonable to assume that the detector components should be ready for integration at the beginning of 2023. • This leaves approximately 30 months for the bulk production of ~10K modules. • We are starting to produce a detailed production plan based on these dates and the aspirations of the different FA.

  6. INFN Contributions (Pixel and common items) • 3D Pixel sensors  RD_FASE2 • Favourite technology in Layer 0/1 • Partnership with FBK • Bump-bonding  RD_FASE2 • Indiumthermo-compressionprocesswithSelexES • Exploring out sourcing for Flip-chip • Pixel module assembly/testing  RD_FASE2 • Multi module read-out and DAQ  RD_FASE2 • Cooling system  RD_FASE2 • Pixel R/O chip (RD53)  CSN5 • CMOS sensors (presently with STM)  HVR_CCPD in CSN5 • Simulation & tracking Attivita’ fortementeinterconnesse traigruppiitaliani. • 2016 Milestones • 31-07-2016: Caratterizzazionein clean room di dispositiviplanari e 3D • 30-11-2016: Test in laboratorio di moduli 3D • 30-11-2016: Definizionelayout per pixel planari e 3D compatibili con RD53

  7. Richieste 2016 Ordini per Sensori e BumpBonding a seguireneiprossimimesi.

  8. INFN Contributions in ITK Responsibilities in ITk (https://twiki.cern.ch/twiki/bin/viewauth/Atlas/ITkPixelOrganization) • Paolo Morettini(Ge) – ITk Pixel Project Leader • Leonardo Rossi (Ge) – ITkInstitute Board Chair • DaniloGiugni (Mi) – ITk Pixel Project Engineer • Claudia Gemme (Ge) – ITk Layout TF co-chair • INFN proposed aspiration: • Pixel: design, production and test of all modules for the innermost two layers (~10% of all modules) including Sensors, Bump-bonding, Flex+WB (including Flex production), Irradiation+Beam tests; mechanical supports for innermost layers and loading of them. • Italian cluster should work together to share construction of the innermost layers. • Contribution to DAQ (software, firmware), voltage distribution system (PP2) and ITk cooling system.

  9. Quick updates • Elettronica** • Sensori 3D (comuni a CMS) • Ibridizzazione: bump-bonding@Selexe accoppiamentocapacitivo • Cooling • Simulazioni

  10. Multi-module setup • Hardware and software per laboratory test are a key ingredient to sustain such a large module production. • Critical also in Italy to be able to produce/qualify modules and load/integrate them on local supports. • Profiting of IBL (and L2/L1 on-going upgrades) experience in Read-Out Card design/production/qualification. • The idea is to produce a table top card, replacing the ROC+BOC current pit implementation: • ROD/BOC table-top

  11. Roadmap to Layout Workshop

  12. Multi-module setup • Table-Top (bladeboard) board under production: 2 prototypes by July 2016 • First tests will be concentrated on the IBL BOC-ROD FW compatibility • Main tests on July-September 2016 • Additional test board production by end of November (order placement) • 2 to 4 boards • Estimated costs: • Design and prototype submission: ≈7k€ • single board cost: ≈3k€ (the Kintex7 only is around 1.5k USD) Richiestasblocco 20 kEuro a Bologna

  13. 3D sensors • Requisiti: • Resistenzaalleradiazionifino a 2x1016neq/cm2 • Material budget ridotto • Pitch 25x100 o 50x50 mm2

  14. New 3D pixels: fabrication SiSi P- high Wcmwafer p++ lowWcmwafer Metal to be deposited after thinning Handle wafer to be thinned down • Thin sensors on support wafer (SiSi) • Ohmic columns/trenches depth > active layer depth (for bias) • Junction columns depth < active layer depth (for high Vbd) • Reduction of hole diameters to ~5 um • Holes (at least partially) filled with poly-Si

  15. New 3D pixels: design and simulations Thickness = 150 µm N+ col. depth = 130 µm 50 x 50 25 x 100 L~28 um L~35 um All designs assuming a column diameter of 5 mm • 50x50 design is safe • 25x100 is risky … • (new ideas for bump pad to be tested) • Capacitance compatible with RD53 specs • Initial breakdown voltage high enough

  16. 3D Pixel Wafer Layout Final version Many different pixel geometries and pitch variations: STRIP • FE-I4 • 50 x 250 (2E) std • 50 x 50 (1E) • 25 x 100 (1E and 2E) • 25 x 500 (1E) • FE-I3 • 50 x 50 (1E) • 25 x 100 (1E and 2E) • PSI46dig • 100 x 150 (2E and 3E) std • 50 x 50 (1E and 2E) • 50 x 100, 100 x 100 (2E + 4E) • 50 x 100, 100 X 150(2E + 6E) • 25 x 100 (1E and 2E) • FCP • 30 x 100 (1E) • RD53 • 50 x 50 (1E) • 25 x 100 (1E) • 25 x 100 (2E) PSI46 dig FE-I4 RD53 big FE-I3 RD53 small STRIP FCP STRIP FCP STRIP + Test structures (strip, diodes, etc)

  17. Electrical characterization Numbers of good detectors per type on 9 wafers • Goodelectricalcharacteristics • in terms of leakagecurrent, • breakdown voltage and • capacitance, in goodagreement • with simulations • ProcessYield ~38% on large sensors (FEI4), >60% on allothers • Best twowafers (76&78) atSelex for bumpbonding

  18. Bump-bonding • Requirements/challenges: • 5x bump density of current IBL  120 k-bumps/chip FEI4 size • Optimize the process on dummies (produced by FBK), studying bump height, size and the process parameters as pressure and temperature. • Visual, mechanical and electrical test of the parts and assemblies. • Bump deposition on 12-inch electronics and 8-inch sensors wafers (was 8” and 6”) • Optimize the process on dummy supports • Wafers and deposition masks procured: test uniformity of bumps deposition. • Handling of thin electronics (100 mm has been achieved for few FEI4 test modules). • Indium bumps have an easier process that does not need temporary support wafer competitive for innermost layers • 10x total surface (14-18 m2vs current pixel of 1.7): • Need to optimize production flows and reduce bottle-necks as Flip-chip  outsourcing ? • We are working with Selex for the R&D phase and to qualify it as vendor.

  19. Bump-bonding@Selex: resistive chains • Resistance of 124 chains, 172 bumps each • X-rays: • Bump shape is elliptic in the FE corners

  20. Bump-bonding@Selex: resistive chains • Very promising results from first resistive chain tests on 6”: • Bumps resistivity as expected • No open among 64k bumps (3 chips) • No indication of shorts (either by X-rays or R measurement) • Mechanical tests with thermal cycles on module-like structure are fine. • Flip-chip planarity needs to be improved. • Next steps: • Resistive chain QA with 12” wafers • … until high pitch density is available with real sensors/RD53A

  21. Bump-bonding@Selex: 12” deposition • Bump deposition on 12” bare wafer (just Si, no pattern) with several bumps openings under test • Wafer has been visually analyzed and bumps height measured with a profilometer • preliminary results on bump height (~10 mm) uniformity good (~1 mm) if opening is larger than 16 mm. • Some problems at the photoresist lift-off due to low number of bumps (bump density is nominal but only in spots uniformly distributed over the wafer surface). • Next steps: • More tests needed with high bumps density all over the wafer and daisy chains to measure bump resistivity. • In Genova design of the resistive chains layout on 12”. • Resistive chain QA with 12” Si wafers  not doable at FBK; investigating with TSMC or CEA LETI.

  22. Bump-bonding production • Main steps for the module assembly: • UBM and Bump deposition on 12” (electronics) and 8” (sensors) wafers • Wafer dicing and thinning • Flip-chip  the bottle neck • At least three companies are needed for the Pixel production. • Qualification will happen in 2017. • Our strategy with Selex: • Qualification of the high-density, large wafer size bump deposition. • Qualification also of the flip-chip of thin electronics (this is competitive for the innermost layers where low material budget is even more important) • Discuss with them if they can provide parts for out-sourcing (Zelenograd, Uni Geneva, Barcelona, etc… )

  23. Capacitive Coupling • HV-CMOS sensors are capacitively coupled to the R/O electronics. • To better control the thickness of the capacitance substrate, pillars are deposited on the wafers. Measurement of the height profile of a FEI4 chip after SU8 deposition. Height of pillars is uniform. The residual rounding on top is due to to placement of the pillars on top of 4µm thick metal structures. Irregularities in the profile reflect real thickness difference in the FEI4.

  24. Capacitive Coupling • HV-CMOS sensors are capacitively coupled to the R/O electronics. • To better control the thickness of the capacitance substrate, pillars are deposited on the wafers.

  25. ITk Cooling • Milano is involved in FEM and CO2 test of local support structure. • Genova is involved in the splitting box project and production. Task definition is becoming more clear as the project progresses. PP1 PP2 Plant in USA15 7 Splitting Box Splitting Box Chiller 9 • Common Mechanics group • (Lukasz Zwalinski, Paolo Petagna, … ) • Plant →PP1 • DEMO & BABY DEMO • Detector group • (Danilo Giugni,…) • PP1 → Detector 8 Transfer line 7 Pump 5 3 4 2 1 6 Staves

  26. Simulation • Simulation is critical to prepare Strip and Pixel TDRs. • Some Italian efforts (Pi, Bo) devoted to study performance with quick tools: • Fast PU simulation approach: • Generation of hard particle • Generation of <m> pile-up events • Selection of PU tracks inside a cone • Save and simulate only particles in a cone. • Useful for quick comparisons. • Fast Digitization • Consider the particle path, ignore the energy deposit, but convert the path length in charge directly, create the cluster. • Use to study pixel size, sensor thickness, R/o threshold, etc…

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