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Computer Architecture Lecture 4 17 th May, 2006

Computer Architecture Lecture 4 17 th May, 2006. Abhinav Agarwal Veeramani V. Recap. Simple Pipeline – hazards and solution Data hazards Static compiler techniques – load delay slot, etc. Hardware solutions – Data forwarding, out-of-order execution, register renaming Control hazards

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Computer Architecture Lecture 4 17 th May, 2006

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  1. Computer ArchitectureLecture 417th May, 2006 Abhinav Agarwal Veeramani V.

  2. Recap • Simple Pipeline – hazards and solution • Data hazards • Static compiler techniques – load delay slot, etc. • Hardware solutions – Data forwarding, out-of-order execution, register renaming • Control hazards • Static compiler techniques • Hardware speculation through branch predictors • Structural hazards • Increase hardware resources • Superscalar out-of-order execution • Memory organisation EE Summer Camp '06

  3. Memory Organization in processors • Caches inside the chip • Faster – ‘Closer’ • SRAM cells • They contain recently-used data • They contain data in ‘blocks’ EE Summer Camp '06

  4. Rational behind caches • Principle of spatial locality • Principle of temporal locality • Replacement policy (LRU, LFU, etc.) • Principle of inclusivity EE Summer Camp '06

  5. Outline • Instruction Level Parallelism • Thread-level Parallelism • Fine-Grain multithreading • Simultaneous multithreading • Sharable resources & Non-sharable resources • Chip Multiprocessor • Some design issues EE Summer Camp '06

  6. Instruction Level Parallelism • Overlap execution of many instructions • ILP techniques try to reduce data and control dependencies • Issue out-of-order independent instructions EE Summer Camp '06

  7. Thread Level Parallelism • Two different threads have more independent instructions • Better utilization of functional units • Multi-thread performance is improved drastically EE Summer Camp '06

  8. A simple pipeline EE Summer Camp '06 source: EV8 DEC Alpha Processor, (c) Intel

  9. Superscalar pipeline EE Summer Camp '06 source: EV8 DEC Alpha Processor, (c) Intel

  10. Speculative execution EE Summer Camp '06 source: EV8 DEC Alpha Processor, (c) Intel

  11. Fine Grained Multithreading EE Summer Camp '06 source: EV8 DEC Alpha Processor, (c) Intel

  12. Simultaneous Multithreading EE Summer Camp '06 source: EV8 DEC Alpha Processor, (c) Intel

  13. Out of Order Execution EE Summer Camp '06 source: EV8 DEC Alpha Processor, (c) Intel

  14. SMT pipeline EE Summer Camp '06 source: EV8 DEC Alpha Processor, (c) Intel

  15. Resources – Replication required • Program counters • Register maps EE Summer Camp '06

  16. Replication not required • Register file (rename space) • Instruction queue • Branch predictor • First and second level caches etc. EE Summer Camp '06

  17. Chip multiprocessor • Number of transistors going up • Have more than one core on the chip • These still share the caches EE Summer Camp '06

  18. Some design issues • Trade-off in choosing the cache size • Power and performance • Super pipelining trade-off • Higher clock frequency and speculation penalty + Power • Power consumption EE Summer Camp '06

  19. Novel techniques for power • Clock gating • Run non-critical elements at a slower clock • Reduce voltage swings (Voltage of operation) • Sleep Mode/ Standby Mode • Dynamic Voltage Frequency scaling EE Summer Camp '06

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