Introduction to CMOS VLSI Design Lecture 11: Adders

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### Introduction toCMOS VLSIDesignLecture 11: Adders

David Harris

Harvey Mudd College

Spring 2004

Outline

PGK
• For a full adder, define what happens to carries
• Generate: Cout = 1 independent of C
• G =
• Propagate: Cout = C
• P =
• Kill: Cout = 0 independent of C
• K =

PGK
• For a full adder, define what happens to carries
• Generate: Cout = 1 independent of C
• G = A • B
• Propagate: Cout = C
• P = A  B
• Kill: Cout = 0 independent of C
• K = ~A • ~B

• Brute force implementation from eqns

• Factor S in terms of Cout

S = ABC + (A + B + C)(~Cout)

• Critical path is usually C to Cout in ripple adder

Layout
• Clever layout circumvents usual line of diffusion
• Use wide transistors on critical path
• Eliminate output inverters

• Complementary Pass Transistor Logic (CPL)
• Slightly faster, but more area

• Dual-rail domino
• Very fast, but large and power hungry
• Used in very fast multipliers

• Each sum bit depends on all previous carries
• How do we compute all these carries quickly?

• Critical path goes from Cin to Cout
• Design full adder to have fast carry delay

Inversions
• Critical path passes through majority gate
• Built from minority + inverter
• Eliminate inverter and use inverting full adder

Generate / Propagate
• Equations often factored into G and P
• Generate and propagate for groups spanning i:j
• Base case
• Sum:

Generate / Propagate
• Equations often factored into G and P
• Generate and propagate for groups spanning i:j
• Base case
• Sum:

Valency-2 equation; uses P/G of two smaller groups

Gi-1:0 is simply the carry-in of this stage, ie., Ci

Si = Pi xor Ci = (Ai xor Bi) xor Ci

PG Logic

C4 = G4 + P4 G3:0

Carry-Ripple Revisited

Note: Carry propagates through And/or network instead of MAJ gate network

Carry-Ripple PG Diagram

1-bit prop/gen cell

delay of And/OR in grey cell

Final SUM bit xor

PG Diagram Notation

Generate only

Both Gen/Prop

• Carry-ripple is slow through all N stages
• Carry-skip allows carry to skip over groups of n bits
• Decision based on n-bit propagate signal

Critical path: Generate carry in first bit, then ripple thru next three bits. Then skip next two four-bit stages, then ripple through last stage.

Carry-Skip PG Diagram

For k n-bit groups (N = nk)

Carry-Skip PG Diagram

For k n-bit groups (N = nk)

First, last group ripple

skip thru muxes

Variable Group Size

Delay grows as O(sqrt(N))

Smaller groups at first/last

• Uses higher-valency cells with more than two inputs.

CLA PG Diagram

Collecting Generate/Propagate over many cells

Higher-Valency Cells

Just the recursive definition of Generate

• Trick for critical paths dependent on late input X
• Precompute two possible outputs for X = 0, 1
• Select proper output when X arrives
• Carry-select adder precomputes n-bit sums
• For both possible carries into n-bit group

Carry Select Critical Path

N = adder size in each group, K groups

Tselect = Tpg + [N+(K-2)]TAO + Tmux

Slightly faster than Carry-skip.

For optimal delay, do not want each group to have the same size, want each group to grow in order to match mux select arrival time with carry generation time.

• Factor initial PG and final XOR out of carry-select

• Factor initial PG and final XOR out of carry-select

Adders in Carry-select have redundant logic, factor this out, reduces logic size, delay essentially the same.

Variable Group Size
• Also buffer

noncritical

signals

Observe that buffer is added so that buffer delay is not on critical path!

• Recursive lookahead gives O(log N) delay
• Many variations on tree adders

Buffers not really necessary

Lots of logic levels!

Brent-Kung

• Ideal N-bit tree adder would have
• L = log N logic levels
• Fanout never exceeding 2
• No more than one wiring track between levels
• Describe adder with 3-D taxonomy (l, f, t)
• Logic levels: L + l
• Fanout: 2f + 1
• Wiring tracks: 2t
• Known tree adders sit on plane defined by

l + f + t = L-1

Logic levels

Fanout

Wire tracks

Han-Carlson

Knowles [2, 1, 1, 1]

Half the wires at last stage than Kogge-Stone, but double the loading.

Hybrid Tree/Carry Select
• Hybrid adders use tree-logic to compute the carries, but also use short ripple chains to reduce the number of gates
• Fig 10.39 of the book shows a good example of a sparse tree adder