Agenda

2. 2 Agenda Introduction: Briefing Objectives Technology impacts on testing, characterization and qualification Examine the latest DoD guidance concerning radiation effects qualification for new technologies Discuss Testing & Evaluation infrastructure issues Summary & Conclusions

3. Satellite System Microelectronics Modern satellite system designers would like to use the most advanced commercial circuits and devices to enhance performance and maintain economic viability: Ultra-large Mixed-Signal UDSM ASIC�s System-on-Chip or System-in-Package approaches Next generation FPGA technology, e.g. Xilinx Virtex V DDR2 SDRAM�s G-4 microprocessors Very high speed data buses and I/O�s Ultra-low power technology approaches The size, speed and complexity of these devices and mission lifetimes has raised significant issues WRT technology qualification and radiation response testing, modeling & simulation and characterization. Three points to be made from this chart: Identifies RHM Program investment strategy 2. Identified need for minimum of 150nm technology to support development of all but r-NV-FPGA, however significant benefits in SWAP could be realized through implementation using 90nm technology 3. Need for complex ASIC and very high speed circuits has resulted in change in technical approach. Demonstration of technology with simple array or SRAM no longer acceptable and requires additional effort to support development of ASIC/SOC devices Design flow development Library development Modeling and simulation High speed test capability PDK�s Three points to be made from this chart: Identifies RHM Program investment strategy 2. Identified need for minimum of 150nm technology to support development of all but r-NV-FPGA, however significant benefits in SWAP could be realized through implementation using 90nm technology 3. Need for complex ASIC and very high speed circuits has resulted in change in technical approach. Demonstration of technology with simple array or SRAM no longer acceptable and requires additional effort to support development of ASIC/SOC devices Design flow development Library development Modeling and simulation High speed test capability PDK�s

4. 4 Briefing Objectives The objective of this briefing is to provide a summary of the radiation testing, characterization and qualification challenges engendered by the use of modern microelectronics and photonics technologies. The briefing will: Identify the specific challenges that result from the use of these technologies. Identify shortfalls in the radiation effects qualifications procedures and requirements Provide specific examples of these problems. Identify short-falls in the current testing infrastructure. Discuss current efforts to resolve these problems

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6. 6 Technology Engendered Challenges Reduced feature size and Increased integration density Lower upset thresholds due to reduced operating voltages and nodal capacitance Increased probability of multiple bit upsets due to increased packing density & charge sharing New materials resulting in unknowns concerning radiation response (dose enhancement) and FIT projection (materials physics of failure) Increased circuit complexity Increased number of failure modes, e.g. SEFI Increased difficulty in T&E of all operating modes, e.g. time for complete node coverage approaching infinity Unobservable and uncontrollable states Radiation sensitivity as a function of operation Critical nodes covered by metal layers Added probability of nuclear reactions with metal layers, e.g. low LET particles causing upset through secondary production Increased circuit operating speed Need for higher speed test equipment and/or approaches Test facility arrangements Device temperature control Packaging complexity Issues WRT test species package penetration, e.g. higher beam energy test facilities required Shadowing of critical nodes Modeling and simulation 3-D and mixed-mode models required Over-layer and substrate interaction must be included Simulation time

7. 7 Testing & Qualification Issues Aerospace �New Parts and Materials and Process Technology Insertion Guideline for Space Applications New Technology Evaluation (Aerospace Report ATR-2005(9308-1)� represents the latest and most cogent document that provides guidance concerning the insertion of �new� technologies into space system applications. Document represents the latest and most up-to-date guidance concerning insertion of �new� technologies, however it is already challenged by the issues involved with the use of advanced microelectronic technologies in radiation environments. The following charts will attempt to elucidate a variety of issues that are not currently addressed and have the potential to severely impact the use of �new� technologies for space applications. The RED script identifies proposed additions to the current document and highlight specific areas of concern related to the use of advanced microelectronics for space applications.

8. 8  New Parts and Materials and Process Technology Insertion Guideline for Space Applications New Technology Evaluation (Aerospace Report ATR-2005(9308-1) Section V.A.7- Characterization Testing Requirements Radiation control and verification requirements are essential for space vehicle hardware, and are dependent on their mission environment and operational requirements. The parts, devices, and materials for new technologies must be tested for total ionizing dosage (high and low dose rates), dose-rate upset, survivability and latch-up, displacement damage dosage, and single event effects, including upset, transients, latch-up, functional interrupts, burn-out, gate rupture and neutron induced upset phenomena. Standard industry test methods such as MIL-STD-883 should be used. Reference MIL-STD-1546 Appendix B and MIL-STD-1547 Appendix A for radiation hardness approaches and methodologies.

9. 9 Standards and specifications for total dose testing of devices for use in space are covered by MIL-HDBK-339, MIL-HNBK-814, MIL-HNBK-815, MIL-HNBK-816, ASTM 1892, and MIL-STD-883. Total dose/fluence effects (see curve Figure 2) a. Protons i Multiple energies or extrapolation using non-ionizing energy loss (NIEL) concepts ii. Various fluences to be perceptive to degradation as well as failure b. Electrons (may be eliminated if part is only to be used inside sufficient shielding) i. Multiple energies ii. Various fluences to be perceptive to degradation as well as failure c. Gamma rays i. Various doses to be perceptive to degradation as well as failure d. Annealing i. If annealing effects are expected to play a role, then irradiation and testing must be performed as a function of temperature with no temperature change between irradiation and test e. Electrical bias i. Some CMOS parts are more or less susceptible to total dose/fluence effects depending upon electrical bias �Antifuse� technology susceptibility in either on-state or off-state is unlikely, but must be shown. f. Operating Mode Effects

10. 10 Test and Evaluation Shortfall:Importance of Mode-Specific ResultsExample: State-of-the-art Flash Memory Evaluation

11. 11 State-of-the-art Flash Memory Evaluation

12. 12 Total Ionizing Dose Effects Testing and Characterization must consider both time dependent and dose-rate dependent effects in certain classes of devices, e.g. LDO, hybrids with both CMOS and bipolar chips, etc. Total dose and dose rate response of low dropout voltage regulators� , R. Pease. Et-al

13. 13 New Parts and Materials and Process Technology Insertion Guideline for Space Applications New Technology Evaluation (Aerospace Report ATR-2005(9308-1) Appendix 6- Example of a New Technology Plan for Utilization of a FPGA Single Event Effects Testing Single Event Upset (CMOS and bipolar including HBT and III-IV technologies) Packaging effects Geometry effects BEOL metal over-layer effects (particle penetration and high energy low LET particles) b. Single Event Latchup i. CMOS vulnerable ii. High current states must not affect antifuse reliability c. Single Event Burnout d. Single Event Gate Rupture i. Does this effect impact antifuses? ii. Impact on reliability due to soft and hard breakdown iii. Impact on non-volatile memory technologies retention and endurance e. Single event total dose i. Primarily affects deep sub-micron CMOS ii. Can a heavy ion impact affect an �antifuse� technology? f. Single Event Transients (CMOS and bipolar including HBT and III-V technologies) i. Testing as a function of operating speed ii. Separation of SEU and SET effects g. Single-Event Functional Interrupt (SEFI) i. Interaction of device operation, S/W and H/W

14. 14 SEU - Integration Density Issue Impacting Test and Evaluation Example: State-of-the-art Commercial Memory

15. 15 SEU - Importance of Angular EffectsExample: State-of-the-art FPGA

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17. 17 SER - Complexity Implications Standard microbeam and laser test facilities have similar limitations for range of particle On older technologies, these facilities are used to determine what structure within a device is causing fault/failure New technique (two-photon absorption - TPA) with the laser is being developed, but is still in research phase New test structures built specifically for test may be required Reduced metalization, special packaging, etc.

18. 18 Particle Energy Effects

19. 19 SEE Modeling and Simulation TaskRecent Results SET model improvements to correctly depict impact of operating voltage on transient pulse width response (application of coupled versus decoupled model) SEU prediction to include impact of high-Z metal over-layers on SER predictions Two order of magnitude increase in cross-section was noted in 4Mbit SRAM due to this effect

20. 20 Packaging Implications Macro-beam structure: implies probabilistic chance of hitting a single node that may be sensitive If test is run for SEE, typical heavy ion test run is to 1x 107 particles/cm2. Ex., SDRAM � 512 Mb (5x108 bits plus control areas) If all memory cells are the same, no issue. BUT if there are weak cells how do you ensure identifying them? Control logic may be a very small area of the chip. If you fly 1000 devices, area is no longer �small� Difficult to evaluate clock edge sensitivity of a node Die access (required for most single event testing) Typical heavy ion single event macro-beam simulators have limited energy range Implies limited penetration through packaged device Access to die typically required Overlayers, metalization, etc must be taken into account

21. 21 Packaging Issues � Test Preparation Commercial devices, e.g. SDRAM, use thin small outline package (TSP) or plastic BGA. Majority of SEE test facilities require removal( acid etch, grinding, etc) of packaging material to ensure particle can reach sensitive volume TSOP: Plastic can be removed, but metal lead frame problematic Plastic FCBGA: De-processing impacts mechanical integrity

22. 22 Ions with Energies from 10-100 MeV/nucleonStill Have Considerable LETs

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24. 24 SET - Aeroflex FPGA Showing no Operating Frequency Effects

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26. 26 SET - Operating Speed Implications Characterization of SET transient pulse width versus operating voltage Characterization of SET response as a family of transient pulses of varying width

27. 27 SET - Operating Speed Implications Testing at a remote facility requires highly portable test equipment capable of high-speed measurements Tester needs to be near the device or utilize high-speed drivers Cable runs between the device under test (DUT) and the tester can be up to 75 feet Simple devices like a shift register chain can be tested using bit error rate testers (BERTs) BERTs can run to ~$1M and tend to be very sensitive to problems from shipping At proton test facilities secondaries are generated (neutrons) that can cause failures in the expensive test equipment if they are located near the DUT Self-test techniques for testing devices being developed for shift-registers Modern reconfigurable FPGA-based test boards being developed to test more generic devices

28. 28 SET - Operating Speed Implications Testing in a vacuum chamber implies mechanical, power/thermal, and hardware mounting constraints High-speed devices often mean high power consumption Issue is mounting of DUT in vacuum chamber and removal of thermal heat Can also be a challenge NOT in a vacuum DUT may need to be custom packaged to allow for thermal issues Active system required for removal of heat

29. 29 SEE High Speed Test Capability Development TaskRecent Results Improved high speed test boards through use of r-FPGA - Low-cost disposable (< $2k) capable of 100Mhz - High speed (> 1 GHz) tester - Both based on r-FPGA and will use daughter cards .

30. 30 SEFI - Complexity Implications

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34. 34 SER - Test and Evaluation Shortfall:Difficulties in �LET� and Data ComplexityExample: 1 Gb 90nm Samsung SDRAM

35. 35 Rouges Gallery of RHA Qualification Single Event Degradation (SED)

36. 36 Rouges Gallery of Qualification Issues SED and SEL (redux)

37. 37 Rouges Gallery of Qualification Steady State TID versus Temperature

38. 38 New Parts and Materials and Process Technology Insertion Guideline for Space Applications New Technology Evaluation (Aerospace Report ATR-2005(9308-1) Appendix 6- Example of a New Technology Plan for Utilization of a FPGA Combined Effects Testing a. Total dose combination of protons and gammas b. Does stress (thermal, mechanical, electrical, etc) affect vulnerability to total dose/fluence? c. Does single event effect vulnerability depend upon total dose/fluence? d. Does single event effect vulnerability depend upon stress (thermal, mechanical, electrical, etc)? 

39. 39 Present Infrastructure Issues Summary Shortfalls exist in all of the previously identified areas impact ability to test, characterize, model/simulate and qualify advanced microelectronics for high reliability space and missile system applications. Cases in-point include: Impact of new materials and manufacturing methods on long term radiation response SEFI in deep-submicron microprocessors, micro-controllers, SDRAM and other complex Testing at operating speed for SET characterization and SER prediction. Test fidelity issues resulting from facility beam energy limitations SEE strike angle dependence SEU and SEL caused by very high energy proton interaction with high-Z metal layers Modeling and simulation fidelity; 3-D models required for deep-submicron devices Programs exist to address these issues but the level of investment is not keeping pace with the complexity and number and problems identified

40. 40 Government and Commercial Organization Initiatives & Programs DoD/DoE Activities: AF Space and Missile System Center and the Aerospace Corporation new technologies qualification guideline and other documents Other DoD organizations are investigating SEE generation, modeling and mitigation including USN, AFRL, MDA, SNL, NSWC, etc. SEE performance now included in existing and planned space and missile systems specifications. Enhanced modeling and simulation efforts are underway Slow but perceptible recognition by military avionics community NASA & FAA Activities: NASA in collaboration with ESA are supporting a robust test and characterization program. FAA sponsored SEE testing of commercial avionics systems has identified issues that are being addressed. Commercial Sector Significant activity to develop test and characterization methods to support use of advanced technology for terrestrial applications; impact of atmospheric particles, e.g. neutrons, etc. on high speed server FIT rates. JEDEC T&E guidelines available

41. 41 Summary and Conclusions Serious shortfalls exist concerning our ability to qualify modern microelectronics for space and missile system high reliability applications. Efforts to improve our capability to perform high speed radiation testing, model and simulate the radiation response of complex integrated circuits, access to high beam energy test facilities, etc are ongoing. A new awareness concerning these shortfalls exists but limited resources and the lack of a single point-of-contact are hampering resolution Perhaps it is time to seriously consider the establishment of a oversight group to address these issues in a more coordinated manner.