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Low Power Design of Standard Cell Digital VLSI Circuits. By Siri Uppalapati Thesis Directors: Prof. M. L. Bushnell and Prof. V. D. Agrawal ECE Department, Rutgers University. Talk Outline. Motivation Background Prior Work Proposed Design Flow Results Conclusion and Future Work .

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low power design of standard cell digital vlsi circuits

Low Power Design of Standard Cell Digital VLSI Circuits

By Siri Uppalapati

Thesis Directors:

Prof. M. L. Bushnell and Prof. V. D. Agrawal

ECE Department, Rutgers University

MS Defense: Uppalapati

talk outline
Talk Outline
  • Motivation
  • Background
  • Prior Work
  • Proposed Design Flow
  • Results
  • Conclusion and Future Work

MS Defense: Uppalapati

motivation
Motivation
  • Increasing gate count + increasing clock frequency = increasing POWER
  • Portable equipment runs on battery
  • Power consumption due to glitches can be 30 – 70%

MS Defense: Uppalapati

motivation chip power density

10000

1000

Rocket

Sun’s

Surface

Nozzle

100

Nuclear

Power Density (W/cm2)

Reactor

8086

10

4004

P6

Hot Plate

8008

Pentium®

8085

386

286

486

8080

1

1970

1980

1990

2000

2010

Year

Motivation: Chip Power Density

Source: Intel

MS Defense: Uppalapati

motivation cont d
Motivation (cont’d…)
  • Present day Application Specific Integrated Circuit (ASIC) chips employ standard cell based design style
    • A quick way to design circuits with millions of gates
  • Existing glitch reduction techniques demand gate re-design: not suitable for acell-based design

MS Defense: Uppalapati

problem statement
Problem Statement
  • To devise a glitch suppressing methodology after the technology mapping phase
    • Without requiring cell re-design
    • Without violating circuit delay constraints

Design Entry

Technology

Mapping

Layout

MS Defense: Uppalapati

talk progress
Talk Progress
  • Motivation
  • Background
  • Prior Work
  • Proposed Design Flow
  • Results
  • Conclusion and Future Work

MS Defense: Uppalapati

power dissipation in cmos circuits 0 25
Power Dissipation in CMOS Circuits (0.25µ)

Ptotal = CL VDD2 f01 + tscVDD Ipeak f01+VDDIleakage

CL

%75

%20

%5

MS Defense: Uppalapati

slide9

Glitches?

  • Unnecessary transitions
  • Occur due to differential path delays
  • Contribute about 30-70% of total power consumption

Delay =1

2

2

MS Defense: Uppalapati

standard cell based style
Standard Cell Based Style
  • Standard cells organized in rows (and, or, flip-flops, etc.)
  • Cells made as full custom
    • All cells of same height
  • Reasonable design time
    • Due to automatic translation

from logic level to layout

Routing

Cell

IO cell

MS Defense: Uppalapati

talk progress11
Talk Progress
  • Motivation
  • Background
  • Prior Work
  • Proposed Design Flow
  • Results
  • Conclusion and Future Work

MS Defense: Uppalapati

prior work
Prior Work
  • Existing glitch reduction techniques
    • Low power design by hazard filtering [Agrawal, VLSI Design ’97]
    • Reduced constraint set linear program [Raja et al., VLSI Design ’03]
    • CMOS circuit design for minimum dynamic power and highest speed [Raja et. al., VLSI Design ’04]
  • Optimization of cell based design
    • Cell library optimization [Masgonty et al., PATMOS ’01]
    • Cell selection [Zhang et al., DAC ’01)]

MS Defense: Uppalapati

prior work hazard filtering
Prior Work: Hazard Filtering

Reference: V. D. Agrawal, “Low Power Design by Hazard Filtering”, VLSI Design 1997

  • Glitch is suppressed when the inertial delay of gate exceeds the differential input delays.
  • Re-design all gates in the circuit for inertial delay > differential delay

3

2

Filtering Effect of a gate

MS Defense: Uppalapati

prior work a reduced constraint set lp model for glitch removal
Prior Work: A Reduced Constraint Set LP Model for Glitch Removal

Reference: T. Raja, V. D. Agrawal and M. L. Bushnell, “Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program”, VLSI Design ‘2003

  • Gate variables d4..d12
  • Buffer Variables d15..d29
  • Corresponding window variables t4..t29 and T4..T29.

MS Defense: Uppalapati

prior work a reduced constraint set lp model for glitch removal cont d
Prior Work: A Reduced Constraint Set LP Model for Glitch Removal (cont’d…)
  • Objective function: Minimize sum of buffer delays inserted
  • Glitch removal constraint:
  • Maxdelay constraint:
  • Transistor sizing or other procedures used to implement these delays

Objective: minimize Σdj all buffers j

dg > Tg – tg all gates g

TPO > maxdelay

MS Defense: Uppalapati

prior work cell library optimization
Prior Work: Cell Library Optimization

Reference: J. M. Masgonty, S. Cserveny, C. Arm and P. D. Pfister, “Low-Power Low-Voltage Standard Cell Libraries with a Limited Number of Cells”, PATMOS ‘01

  • Limited logic functions with greater cell sizing can result in 20 - 25% savings in power
  • Transistor sizing for
    • Multiple driving strength
    • Balanced rise and fall times
  • Power optimized by minimizing parasitic capacitances
  • Limitations:
    • Discrete set of varieties
    • Optimization of cells cannot be circuit-specific

MS Defense: Uppalapati

prior work cell selection
Prior Work: Cell Selection

Reference: Y. Zhang, X. Hu and D. Z. Chen, “Cell Selection from Technology Libraries for Minimizing Power”, DAC ‘01

  • Mixed Integer Linear Program (MILP) to select from different realizations of cells such that power consumption is minimized without violating delay constraints
    • Sum of dynamic and leakage power is minimized
  • A set of variables for each cell to support different
    • Sizes
    • Supply voltages
    • Threshold voltages
  • Achieved 79% power saving on an average
  • Limitation: depends on diversity of the cell library

MS Defense: Uppalapati

talk progress18
Talk Progress
  • Motivation
  • Background
  • Prior Work
  • Proposed Design Flow
  • Results
  • Conclusion and Future Work

MS Defense: Uppalapati

new glitch removing solution
New Glitch Removing Solution
  • Balanced the differential delays at cell inputs:
    • Using delay elements called Resistive Feedthrough cells
  • Automated the delay element
    • Generation
    • Insertion into the circuit

MS Defense: Uppalapati

proposed design flow
Proposed Design Flow
  • Modified linear program
  • Resistive feed though cell generation:
    • Fully automated
    • Scalable to large ICs
  • Layout generation of modified netlist
    • Can use any place-and-route tool

Design Entry

Tech.

Mapping

Remove

Glitches

Layout

MS Defense: Uppalapati

first attempt did not work modified linear program
First Attempt – Did not work: Modified Linear Program
  • Changes from Raja’s linear program:
    • Gate delays – constants
    • Wire delays – only variables
  • Constrained solution space
  • Large number of buffers inserted
  • Buffers consume power
    • may exceed the power saved

MS Defense: Uppalapati

comparison of delay elements
Comparison of Delay Elements
  • Resistor shows
    • Maximum delay
    • Minimum power and area per unit delay
    • Hence, best delay element
  • Resistive feed through cell
    • A fictitious buffer at logic level

III. Polysilicon

resistor

I. Inverter pair

II. n diffusion

capacitor

IV. Transmission

gate

MS Defense: Uppalapati

resistive feed through cell
Resistive Feed-through Cell
  • A parameterized cell
  • Physical design is simple – easily automated
  • No routing layers(M2 to M5) used – not an obstruction to the router

R = R□*(length of poly)

Width of poly

MS Defense: Uppalapati

rc delay model
RC Delay Model
  • Used to find the resistance value for a given delay
  • Delay depends on load capacitance
    • Number of fan-outs
  • SPECTRE simulations done for varying R and CL values
  • CL is varied in steps of transistor pairs

R

Vin

CL

MS Defense: Uppalapati

rc delay model cont d
RC Delay Model (cont’d…)
  • CL varies during transition
    • Model not perfectly linear
  • Measured data stored as a 3D lookup table
  • Average of signal rise and fall delays
  • Linear interpolation between two points

TPLH + TPHL

TP =

2

MS Defense: Uppalapati

detailed design flow
Detailed Design Flow

Design Entry

Find delays from LP

Find resistor values from lookup table

Tech.

Mapping

Remove

Glitches

Generate feed through cells and modify netlist

Layout

MS Defense: Uppalapati

talk progress27
Talk Progress
  • Motivation
  • Background
  • Prior Work
  • Proposed Design Flow
  • Results
  • Conclusion and Future Work

MS Defense: Uppalapati

experimental procedure
Experimental Procedure
  • Extract cell delays from initial layout
    • SPECTRE simulation
  • LP solver: CPLEX in AMPL
    • C program to generate the input files
  • Physical design of feed through cells and insertion of fictitious buffers
    • PERL script
  • Place-and-Route
    • Silicon Ensemble from Cadence

MS Defense: Uppalapati

power estimation
Power Estimation
  • Logic level
    • Event-driven delay simulator to count the transitions
    • Power α # transitions × # fanouts
  • Post layout
    • SPECTRE simulator to measure current through the power rail
    • Average power calculated by integration

MS Defense: Uppalapati

results
Results

Circuit

Area Overhead(%)

Power Saved(%)

Power Saved(%)

MS Defense: Uppalapati

glitch elimination on net86 in the 4bit alu
Glitch Elimination on net86 in the 4bit ALU

Source: Post layout simulation in SPECTRE

MS Defense: Uppalapati

energy saving in 4 bit alu
Energy Saving in 4 bit ALU

MS Defense: Uppalapati

layouts of c880
Layouts of c880

Original layout of c880

Optimized layout of c880

MS Defense: Uppalapati

talk progress34
Talk Progress
  • Motivation
  • Background
  • Prior Work
  • Proposed Design Flow
  • Results
  • Conclusion and Future Work

MS Defense: Uppalapati

conclusions
Conclusions
  • Successfully devised a glitch removal method for the standard cell based design style
    • Does not require re-design of the mapped cells
    • Does not increase the critical path delay
    • Scalable with technology
  • The modified design flow is well automated
    • Maintains the low design time of this style
  • On an average
    • Dynamic power saving: 41%
    • Area overhead: 60%

MS Defense: Uppalapati

future work
Future Work
  • Diverse target cell library
    • Cells of different propagation delays
    • LP model needs to be changed
    • Might become an ILP
  • 70% of necessary delays below 2 ns
    • Interconnect delays can be used
    • Placement and routing algorithms need to be controlled
    • An NP complete problem

MS Defense: Uppalapati

future work contd
Future Work (contd…)

Reference: 1997 International Technology Roadmap for Semiconductors

MS Defense: Uppalapati

references
References
  • V. D. Agrawal, “Low Power Design by Hazard Filtering”, VLSI Design 1997
  • T. Raja, V. D. Agrawal and M. L. Bushnell, “Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program”, VLSI Design 2003
  • Y. Zhang, X. Hu and D. Z. Chen, “Cell Selection from Technology Libraries for Minimizing Power”, DAC 2001
  • J. M. Masgonty, S. Cserveny, C. Arm and P. D. Pfister, “Low-Power Low-Voltage Standard Cell Libraries with a Limited Number of Cells”, PATMOS 2001

MS Defense: Uppalapati

slide39

THANK YOU

MS Defense: Uppalapati

prior work existing low power design techniques
Prior Work: Existing Low Power Design Techniques

HW/SW co-design, Custom ISA,

Algorithm design

System

Architectural

Scheduling, Pipelining, Binding

RT - Level

Clock gating, State assignment, Retiming

Logic

Logic restructuring, Technology mapping

Fan-out Optimization, Buffering, Transistor

sizing, Glitch elimination

Physical

MS Defense: Uppalapati

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