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Chapter 2 Manufacturing Process and CMOS Circuit Layout 1 st rev. : March 7, 2003 2 nd rev. : April 10, 2003 CMOS Process A Modern CMOS Process Dual-Well Trench-Isolated CMOS Process The Manufacturing Process

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chapter 2

Chapter 2

ManufacturingProcess

and

CMOS Circuit

Layout

1st rev. : March 7, 2003

2nd rev. : April 10, 2003

a modern cmos process
A Modern CMOS Process

Dual-Well Trench-Isolated CMOS Process

the manufacturing process
The Manufacturing Process

For a great tour through the IC manufacturing process and its different steps, check

www.fullman.com/semiconductors/semiconductors.html

patterning of sio2
Patterning of SiO2

Chemical or plasma

etch

Si-substrate

Hardened resist

SiO

2

(a) Silicon base material

Si-substrate

Photoresist

SiO

2

(d) After development and etching of resist,

chemical or plasma etch of SiO

2

Si-substrate

Hardened resist

(b) After oxidation and deposition

SiO

of negative photoresist

2

Si-substrate

UV-light

Patterned

(e) After etching

optical mask

Exposed resist

SiO

2

Si-substrate

Si-substrate

(f) Final result after removal of resist

(c) Stepper exposure

photo lithographic process
Photo-Lithographic Process

optical

mask

oxidation

photoresist

photoresist coating

removal (ashing)

stepper exposure

Typical operations in a single

photolithographic cycle (from [Fullman]).

photoresist

development

acid etch

process

spin, rinse, dry

step

recurring process steps
Recurring Process Steps
  • Diffusion and Ion Implantation: change dopant concentration of some parts of the material.
  • Deposition: Silicon Nitride Si3N4 (CVD, chemical vapor deposition, Polysilicon (polycrystalline silicon), Aluminum
  • Etching: Si2O (acid), Plasma etching (dry etching)
  • Planarization: Chemical-mechanical planarization (CMP) on top of Si2O before deposition of an extra metal layer.
cmos process at a glance

Define active areas

Etch and fill trenches

Implant well regions

Deposit and pattern

polysilicon layer

Implant source and drain

regions and substrate contacts

Create contact and via windows

Deposit and pattern metal layers

CMOS Process at a Glance
cmos process walk through

p-epi

(a) Base material: p+ substrate

with p-epi layer

+

p

Si

N

3

4

SiO

(b) After deposition of gate-oxide and

2

p-epi

sacrificial nitride (acts as a

buffer layer)

+

p

(c) After plasma etch of insulating

trenches using the inverse of

the active area mask

p

+

CMOS Process Walk-Through
cmos process walk through10

SiO

2

(d) After trench filling, CMP

planarization, and removal of

sacrificial nitride

n

(e) After n-well and

V

adjust implants

Tp

p

(f) After p-well and

V

adjust implants

Tn

CMOS Process Walk-Through
cmos process walk through11

poly(silicon)

(g) After

polysilicon deposition

and etch

n

+

+

p

(h) After

n

+

source/drain and

p

+

source/drain implants. These

steps also dope the polysilicon.

SiO

2

(i) After deposition of SiO

2

insulator and contact hole etch.

CMOS Process Walk-Through
cmos process walk through12

Al

(j) After deposition and

patterning of first Al layer.

Al

SiO

2

(k) After deposition of SiO

2

insulator, etching of via’s,

deposition and patterning of

second layer of Al.

CMOS Process Walk-Through
3 d perspective
3D Perspective

Polysilicon

Aluminum

cmos process layers

Layer

Color

Representation

Well (p,n)

Yellow

Active Area (n+,p+)

Green

Select (p+,n+)

Green

Polysilicon

Red

Metal1

Blue

Metal2

Magenta

Contact To Poly

Black

Contact To Diffusion

Black

Via

Black

CMOS Process Layers
sticks diagram

V

DD

3

Out

In

1

GND

Stick diagram of inverter

Sticks Diagram
  • Dimensionless layout entities
  • Only topology is important
  • Final layout generated by “compaction” program
design rules23
Design Rules
  • Interface between designer and process engineer
  • Guidelines for constructing process masks
  • Unit dimension: Minimum line width
    • scalable design rules: lambda parameter
    • absolute dimensions (micron rules)
design rule checker on line check
Design Rule Checker (on-line check)

poly_not_fet to all_diff minimum spacing = 0.14 um.

cmos layout of complexe gate from chapter 6 slides and insert d

CMOS Layout ofComplexe Gate:From Chapter 6 Slides and Insert D

Designing CombinationalLogic Circuits

March 28, 2003

complex cmos gate

B

A

C

D

Complex CMOS Gate

OUT = D + A • (B + C)

A

D

B

C

constructing a complex gate
Constructing a Complex Gate

OUT = D + A • (B + C)

stick diagrams

V

V

DD

DD

Stick Diagrams

Contains no dimensions

Represents relative positions of transistors

Inverter

NAND2

Out

Out

In

A

B

GND

GND

stick diagrams36

X

PUN

C

i

VDD

X

B

A

j

A

PDN

B

GND

C

Stick Diagrams

Logic Graph

A

j

C

B

X = C • (A + B)

C

i

A

B

PUN: Pull-up Network, PDN: Pull-down Network

two versions of c a b

A

C

B

A

B

C

VDD

VDD

X

X

GND

GND

Two Versions of C • (A + B)

Two Strips Line of Diffusions

One Strip Line of Diffusions

oai22 logic graph
OAI22 Logic Graph

X

PUN

A

C

D

C

B

D

VDD

X

X = (A+B)•(C+D)

C

D

B

A

A

B

PDN

A

GND

B

C

D

example x ab cd
Example: x = ab+cd

Euler Paths

For both PUD

and PDN

cell design
Cell Design
  • Standard Cells (gate collection)
    • General purpose logic
    • Can be synthesized
    • Same height, varying width
  • Datapath Cells
    • For regular, structured designs (arithmetic)
    • Includes some wiring in the cell
    • Fixed height and width
standard cell layout methodology 1980s
Standard Cell Layout Methodology – 1980s

VDD

Routing

channel

VDD

signals

GND

standard cell layout methodology 1990s
Standard Cell Layout Methodology – 1990s

Mirrored Cell

No Routing

channels

VDD

VDD

M2

M3

GND

GND

Mirrored Cell

standard cells

V

DD

Standard Cells

N Well

Cell height 12 metal tracks

Metal track is approx. 3 + 3

Pitch = repetitive distance between objects

Cell height is “12 pitch”

Out

In

2

Rails ~10

GND

Cell boundary

standard cells45

V

V

DD

DD

Standard Cells

With minimaldiffusionrouting

With silicided diffusion

Out

In

Out

In

GND

GND

standard cells46

V

DD

Standard Cells

2-input NAND gate

A

B

Out

GND

slide47

CMOS Fabrication and Layout

  • See the supplement data in Web!
  • http://access.ee.ntu.edu.tw