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Address Translation. Translation table. Data reads or writes (untranslated). Recall from Last Time…. Translation tables are implemented in HW, controlled by SW. Virtual addresses. Physical addresses. This Lecture…. Different translation schemes Base-and-bound translation Segmentation

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Presentation Transcript
recall from last time
Translation table

Data reads or writes

(untranslated)

Recall from Last Time…
  • Translation tables are implemented in HW, controlled by SW

Virtual

addresses

Physical

addresses

this lecture
This Lecture…
  • Different translation schemes
    • Base-and-bound translation
    • Segmentation
    • Paging
    • Multi-level translation
    • Paged page tables
    • Hashed page tables
    • Inverted page tables
assumptions
Assumptions
  • 32-bit machines
  • 1-GB RAM max
base and bound translation
Base

+

Physical address

>

Error

Bound

Base-and-Bound Translation
  • Each process is loaded into a contiguous region of physical memory
  • Processes are protected from one another

Virtual address

base and bound translation1
base = 6250

code

data

stack

6250 + bound

Base-and-Bound Translation
  • Each process “thinks” that it is running on its own dedicated machine, with memory addresses from 0 to bound

Virtual addresses

Physical addresses

0

code

data

stack

bound

base and bound translation2
Base-and-Bound Translation
  • An OS can move a process around
    • By copying bits
    • Changing the base and bound registers
pros and cons of base and bound translation
Pros and Cons of Base-and-Bound Translation

+ Simplicity

+ Speed

- External fragmentation: memory is wasted because the available memory is not contiguous for allocation

- Difficult to share programs

  • Each instance of a program needs to have a copy of the code segment
pros and cons of base and bound translation1
Pros and Cons of Base-and-Bound Translation

- Memory allocation is complex

  • Need to find contiguous chunks of free memory
  • Reorganization involves copying

- Does not work well when address spaces grow and shrink dynamically

segmentation
Segmentation
  • Segment: a region of logically contiguous memory
  • Segmentation-based transition: use a table of base-and-bound pairs
segmentation illustrated
0x0

0x0

code

data

0x4ff

0x6ff

0x1000

data

0x14ff

0x2000

stack

0x2fff

0x3000

stack

0x3fff

0x4000

code

0x46ff

Segmentation Illustrated

Virtual addresses

Physical addresses

segmentation diagram
up to 30 bits

30 bits

Physical seg base

Seg bound

22 entries

Physical seg base

Seg bound

Physical seg base

Seg bound

up to 30 bits

+

Phy addr

log2(1GB) = 30 bits for 1GB of RAM

32 - 30 = 2 bits

for 32-bit machines

>

Error

Segmentation Diagram

Virt seg #

Offset

segmentation diagram1
0x4000

0x700

code

0x0

0x500

data

0x2000

0x1000

stack

+

0x2200

>

Segmentation Diagram

2

0x200

segmentation translation
Segmentation Translation
  • virtual_address = virtual_segment_number:offset
  • physical_base_address = segment_table[virtual_segment_number]
  • physical_address = physical_base_address:offset
pros and cons of segmentation
Pros and Cons of Segmentation

+ Easier to grow and shrink individual segments

+ Finer control of segment accesses

  • e.g., read-only for shared code segment

+ More efficient use of physical space

+ Multiple processes can share the same code segment

- Memory allocation is still complex

  • Requires contiguous allocation
paging
Paging
  • Paging-based translation: memory allocation via fixed-size chunks of memory, or pages
  • The memory manager uses a bitmap to track the allocation status of memory pages
  • Translation granularity is a page
paging illustrated
Paging Illustrated

Virtual addresses

Physical addresses

0x0

0x0

0x1000

0x1000

0x2000

0x2000

0x3000

0x3000

0x3fff

0x4000

paging diagram
32 – 12 = 20 bits for 32-bit machines

log2(4KB) = 12 bits for 4-KB pages

Virtual page number

Physical page number

Offset

Offset

Page table size

>

Physical page number

220 entries

Physical page number

Physical page number

Error

log2(1GB) = 30 bits for 1GB of RAM

Paging Diagram
paging example
0

4

0x400

0x400

4

>

0

4

1

0

2

2

Paging Example
paging translation
Paging Translation
  • virtual_address = virtual_page_number:offset
  • physical_page_number = page_table[virtual_page_number]
  • physical_address = physical_page_number:offset
pros and cons of paging
Pros and Cons of Paging

+ Easier memory allocation

+ Allows code sharing

- Internal fragmentation: allocated pages are not fully used

- The page table size can potentially be very large

  • 32-bit architecture with 1-KB pages can require 4 million table entries
multi level translation
Multi-Level Translation
  • Segmented-paging translation: breaks the page table into segments
  • Paged page tables: Two-level tree of page tables
segmented paging
30 bits for 1-GB RAM

32 - 3 - 12 = 17 bits

Page table base

Page table bound

23 entries

Page table base

Page table bound

Page table base

Page table bound

12 bits for 4-KB pages

18 bits

Seg #

Virt page #

Offset

num of

entries

defined by

bound; up

to 217

entries

+

Phy page #

log2(6 segments)

= 3 bits

Phy page #

Phy page #

>

Error

Segmented Paging
segmented paging1
32 – 3 – 12 = 17 bits

217

Seg #

Virt page #

Offset

Page table size

>

Phy page #

Phy page #

Phy page #

Phy page #

Offset

Error

log2(1GB) = 30 bits for 1GB of RAM

Segmented Paging
segmented paging translation
Segmented Paging Translation
  • virtual_address = segment_number:page_number:offset
  • page_table = segment_table[segment_number]
  • physical_page_number =

page_table[page_number]

  • physical_address = physical_page_number:offset
pros and cons of segmented paging
Pros and Cons of Segmented Paging

+ Code sharing

+ Reduced memory requirements for page tables

- Higher overhead and complexity

- Page tables still need to be contiguous

- Each memory reference now takes two lookups

paged page tables
12 bits

Page table address (30 bits)

Phy page num

12 bits for 4-KB pages

Page table address

Phy page num

Page table address

Phy page num

212

entries

28

entries

Phy page num (18 bits)

Offset

Paged Page Tables

Page table num

Virt page num

Offset

paged page table translation
Paged Page Table Translation
  • virtual_address = outer_page_num:inner_page_num:offset
  • page_table = outer_page_table[outer_page_num]
  • physical_page_num = inner_page_table[inner_page_num]
  • physical_address = physical_page_num:offset
pros and cons of paged page tables
Pros and Cons of Paged Page Tables

+ Can be generalized into multi-level paging

- Multiple memory lookups are required to translate a virtual address

  • Can be accelerated with translation lookaside buffers (TLBs)
    • Stores recently translated memory addresses for short-term reuses
hashed page tables
Hashed Page Tables
  • Physical_address = hash(virtual_address)
    • Ideal for large virtual addresses (e.g. the current 64-bit architecture). Why?

+ Conceptually simple

- Need to handle collisions

- Need one hash table per address space

inverted page table
Inverted Page Table
  • Traditional paging system
    • One slot for each virtual address, used or not
    • A very large number of total table entries
  • Inverted page table
    • One entry per physical page
    • One page table for the whole system
  • Used in some 64-bit systems (UltraSPARC, PowerPC, etc)
inverted page table1
Inverted Page Table
  • Example (IBM RT):
    • Virtual address:
    • Page table entry
    • For each address:
      • Search the page table entry for
        • If found, is the physical address
        • If not found, address not in physical memory
  • Table search can be time consuming. It is typically based on hashing.
search in inverted page table example
Search in inverted page table example
  • Steps:
    • Hash PID and virtual page number for an index to HAT
    • Lookup physical frame number in the HAT
    • Look at the inverted page table entry. If yes, done; Otherwise, follow the hash chain
inverted page table2
Inverted Page Table

+ The number of page table entry is proportional to the size of physical RAM

- Collision handling

- Hard to do shared memory (multiple pid mapping to the same physical address).

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