Design of R1,R2 and W1

1. DESIGN OF R1,R2 and W1 Date:-14/04/2020 Time:-1:00 pm By Huirem Bharat Meitei Ernl No:-19405004 PhD VLSI (ECE) Supervisor Dr.Manoj Kumar Assistant Professor Department of Electronics &Communication NIT Manipur

2. Contents • Introduction • Systolic Array Design Methodology • DG and Basic Vectors • Design R1 • Design R2 • Design W1 • Alternative Design • Conclusion

3. Introduction • In order to design different Systolic Architectures like R1,R2,W1,B1,F etc. • Follow Design methodology. • Construct the Systolic Architecture accordingly

4. Systolic Array Design Methodology Represent the Algorithm as a Dependence Graph Applying Projection, Processor, and Scheduling Vectors(Space-Time Representation) Edge Mapping Construct the Final Systolic Architecture

5. DG and Basic Vectors • Projection vector dT= [d1d2] • Processor space vector pT= [p1p2] • Schedule vector sT= [s1s2] • Hardware utilization efficiency: HUE = 1/|sTd| Note:- Processor space vector and the projection vector must be orthogonal to each other. P is orthogonal to d, that is, pTd = 0 Basic Vectors

6. Design R1 Results Stay, Inputs and Weight Move in Opposite Directions STEP 1:- Selection of Projection, Processor, and Scheduling Vectors dT=[1 -1] ,pT=[1 1] ,sT=[1 -1] STEP 2:-Edges Mapping Table:-1 edges mapping of R1 design

7. STEP 3:- Block diagram Fig 1:- Block diagram of R1 Design STEP 4:- low level implementation Fig 2:- Low level implementation of R1 Design

8. Design R2Results Stay, Inputs and Weights Move in the Same Direction but at Different Speeds STEP 1:- Selection of Projection, Processor and Scheduling Vectors dT=[1 -1] pT=[1 1] sT=[2 1] STEP 2:-Edges Mapping Table 2:- Edges mapping of R2 Design STEP 3:- Block diagram Fig 3:- Block diagram of R2 Design

9. Design W1 Weights Stay, Inputs and Results Move in Opposite Directions STEP 1:- Selection of Projection, Processor and Scheduling Vectors dT=[1 0] pT=[0 1] sT=[2 1] STEP 2:-Edges Mapping Table 3:- Edges mapping of W1 Design STEP 3:- Block diagram Fig 4:- Block diagram of W1 Design

10. ALTERNATIVE DESIGN Table 4:- Other alternative Design

11. Conclusion • By Proper Determining of projection vector d, processor space vector pT and scheduling vector sT • Designing of systolic Architecture R1,R2 and W1 is achieved from edges mapping.

12. References • vlsi-digital-signal-processing-keshab-k-parhi • VLSI programming Systolic Designhttp://www.win.tue.nl/~wsinmak/Education/2IMN35/2IMN35-2016-slides-systolic.pdf • Systolic Architecture Design. Lan-DaVan, Ph. D. Department of Computer Science National ChiaoTung University Taiwan,R.O.C.Fall, 2010 4. Why Systolic Architecture? http://www.eecs.harvard.edu/~htk/publication/1982-kung-why-systolic-architecture.pdf

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