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MP3 Player/Boombox. Kevin Davis. Shane Neuville. Dan Chao. Andy Owens. Christopher Tillery ... MP3 decoder startup and control code (VHDL) Input control & user ...

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    1. MP3 Player/Boombox Kevin Davis Shane Neuville Dan Chao Andy Owens Christopher Tillery

    2. Project Objectives Play MP3s off of a CD-Rom Ability to select current track Ability to stop, pause, rewind, and fast forward Interactive LCD display Display artist and song title Display Play Time

    3. Project Components

    4. Software Overview Driver for CD-Rom (VHDL) Driver for LCD (C/Assembly) MP3 decoder startup and control code (VHDL) Input control & user interface (VHDL) DMA Interface (VHDL)

    5. File Storage IDE CD-Rom Drive Store the songs in mp3 format. ATAPI Interface ISO 9660 Interface via Xilinx XCS-10 Mp3 Format CDs Compressed audio allowing more songs per CD. ID3 tags can be utilized to display Artist, Song Title, etc.

    6. FPGA ATAPI Interface DMA interaction will be designed in VHDL. ISO9660 File System also in VHDL FPGA will communicate the Path Table information to the MCU via the SPI interface

    7. ATAPI DMA Communication Setup Sector, Cylinder and Device/Head Communications Assert necessary lines to initiate DMA transfer. Transfer data according timing described in Multiword DMA When transfer is done clear out Status registers

    8. Multiword DMA data transfer

    9. ISO 9660 File Structure

    10. Xilinx XCS10 FPGA Decode controls Arbitrate data transfer from CDROM to Decoder Send data for the LCD to RAM Chip select for RAM and EPROM Simulate I2C to set the mode of our MP3 Decoder

    11. FPGA & EPROM Schematic

    12. I2C Simulation Simulate through FPGA Timing

    13. MAS3587F Setup

    14. MAS3587F Data Transfer

    15. MAS3587F Schematic

    16. LCD Display - 4x20 characters Display ID3 tag information: Song Title, Artist, etc. Playtime and Volume

    17. LCD Serial model 634 Built in Controller Communicates with Processor using RS232 Baud Rate of 9600 Jumper setting allows for 5V TTL signal Backlight powered by 5V source, 300mA 5V source to power LCD electronics

    18. Communicating using RS232 Line from TxD on HC11 to DataIn on LCD RxD tied to high or idle state Data to be sent put in SCDR (Serial Comm. Data Register) Data transfer into transmit data register and output on TxD Baud rate set in Baud Rate Register in HC11 Baud rate set with dip switches on LCD

    19. Control Codes

    20. Characters

    21. Knowing what to display FPGA communicates with processor using SPI Interface State changed by push buttons (play, stop, next, prev) ID3 & Table of Contents data transferred to into RAM from FPGA for LCD display Flash memory will hold user interface software for LCD

    22. Processor Motorola M68HC11E0

    23. Processing Power 16 bit Address Bus 8 bit Data Bus SCI and SPI serial interface SCI interface for LCD Display SPI interface for FPGA and CPU communication

    24. Processor Schematic

    25. Cost Estimates FPGA board: Donated Processor: Donated MP3 Encoder/Decoder: Donated LCD Screen with controller: $80 PCB board: $100 RAM: Donated CD-ROM Drive: Free (used) Speakers: Free (donated) Miscellaneous Parts: $70 Total Estimated Cost: $230

    26. Risks and Contingency Plan Problem with reading CD-Rom Send MP3s through computer serial port LCD malfunction Display just control info and not ID3 tag information Use a simpler LCD model

    27. Division of Labor

    28. Updated Schedule

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