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Oklahoma State University

Oklahoma State University. HIGH TEMPERATURE BIAS GENERATOR DESIGN Presented by : Chris Hutchens. Outline. Transistor The Bias Generator Equation V B1 and V B4 V B3 and V B4 Stacking Low VT and High VT devices Stacking “zero” VT and Low VT devices Start-up Circuit. Background.

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Oklahoma State University

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  1. Oklahoma State University HIGH TEMPERATURE BIAS GENERATOR DESIGN Presented by:Chris Hutchens

  2. Outline • Transistor • The Bias Generator Equation • VB1 and VB4 • VB3 and VB4 • Stacking Low VT and High VT devices • Stacking “zero” VT and Low VT devices • Start-up Circuit

  3. Background 1 plus a small number Square Root of 1 plus a small number Square Root of 1 divided by plus a small number Example Veff difference of two NMOS transistors; Equal ID and S=32 and S=45.

  4. Bias Generator optional Bias VB1 thur VB4 Stack Bias Startup

  5. SOI Square Law

  6. Squqre Law Bias Equation VB1 VB4 M1 M2

  7. Squqre Law Bias Equation Low Headroom

  8. Peregrine 0.5um SOS VB3 and VB2

  9. Peregrine 0.5um SOS VB3 and VB2

  10. Peregrine 0.5um SOS Constant Gain Bias

  11. Peregrine 0.5um SOS Constant Gain Bias

  12. Peregrine 0.5um SOS Constant gm bias

  13. Peregrine 0.5um SOS Constant gm bias

  14. Peregrine 0.5um SOS Startup Circuit 2 Possible Solutions

  15. Peregrine 0.5um SOS Startup Circuit

  16. Startup Circuit Improved Start up Ckt 3rd Leg provides VB3

  17. SOI Subthreshold

  18. SOI Moderate Inversion

  19. SOI PSRR - plus Long Channel Cascode Long Channel

  20. SOI Temperature Considerations

  21. SOI Decouping of V Biases Trim Pot Engineering

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